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16 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE Figure 1.1: An alpha particle hits a CMOS transistor. The particle generates electron-hole pairs in its wake, which effects charge disturbance [MW04] of this current pulse, a transient voltage pulse may appear at the hit node. This is characterized as the fault. There is a fault latency period that defines the time needed for that fault to become an error in the circuit. This will only occur if this transient voltage node changes the logic of a storage element (flip-flop), generating a bit-flip. This bit-flip may generate an error if the content of this flip-flop is used for a certain operation. However, for the application point of view, it is not mandatory that this error is manifested as a failure in the system. There is also an error latency that defines the time needed for that error to become a failure in the system. The common term for any measurable effect Ionization Transient Current Transient Voltage Pulse Fault Effect Figure 1.2: Strike of high energy particle resulted in error(s) Error resulting from the deposition of energy from a single ionizing particle strike, is a Single Event Effect (SEE). The most relevant SEEs are classified in figure 1.3.
1.1. PROBLEMATIC 17 SEE (Single Event Effect) SET (Single Event Transient) SBU (Single Bit Upset) MBU (Multi Bit Upset) SEFI (Single Event Functional Interrupt) SELU (Single Event Latch-Up) SEGR/SEB (Single Event Gate-Rupture/Burnout) SEU (Single Event Upset) Soft Error Hard Error Figure 1.3: Classification of faults on basis of single event effect (SEE) [Pie07]. Single Event Upset (SEU) The SEU is mostly a soft error caused by the transient signal induced by a single energetic particle strike [JES06]. In [Bau05], it is said to occur when a radiation event causes a charge disturbance large enough to reverse or flip the data state of a memory cell, register, latch, or flip-flop. The error is called soft because the device is not permanently damaged by the radiation and when new data is written to the struck memory cell, the device will store it correctly [Bau05]. The SEU is a very serious problem because it is one of the major source of failure in digital systems [Nic10]. It will likely pose serious threats to the future of robust computing [RK09] and require serious attention. It may manifest itself as Single Bit Upset (SBU) or Multiple Bit Upset (MBU). Single Bit Upset (SBU) and Multiple Bit Upset (MBU) An SBU is a single radiation event that results in one bit flip whereas an MBU is a single radiation event that results in more than a single bit being flipped. Each bit flip is essentially an SEU. An SBU and MBU are therefore considered a subset of the SEU. The SBU are usually a major fraction and MBU are usually a small fraction of the total number of observed SEUs. However, the MBU probability is steadily increasing as geometries shrink [BCT08, QGK + 06]. Presently, this thesis is addressing SBUs. In future, methodology will be further extended for addressing MBUs.
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
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3.7. FUNCTIONAL IMPLEMENTATION 67 n
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3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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