Dependable Memory - Laboratoire Interface Capteurs ...

2.4. FT PROCESSOR DESIGN TRENDS 45
Intel 80486
Motorola 68040
AMD 29050
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Power6 [MSSM10, KMSK09, KKS + 07]
Intel 80486
Motorola 68040
AMD 29050
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output
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Intel 80486
Motorola 68040
AMD 29050
Error in any
component
Figure 2.12: The triple-TMR in Boeing 777 [Yeh02]
IBM designs the Power6 processor. It uses inline checkers instead of TMR technique that uses
less power and HW overheads. It has build in self-checking ability in the data and control flow paths.
The residue checking is employed for floating-point unit and logical consistency checkers for control
logic. It has recovery unit which checkpoints after a group of superscalar instructions are completed.
The inline checkers writes into fault isolation register that decides if current state is error free. In case
of error detection, the recovery unit initiates instructions retry recovery. The memory bus including
input-output unit is protected by ECC codes. The L1 cache is protected by simple parity, while L2,
L3 caches and all signals in and out of chip to L3 have ECC protection.
Intel Itanium 9300 Series [Int09]
Intel Itanium 9300 series processors is a high performance processors. The L2, L3 and directory
caches are protected with ECC. It can correct all single bit errors and most double errors. Moreover,
hardware assisted scrubbing support is available for L2, L3 and directory caches. Memory is also
protected against the thermal protection. Here, different thermal sensors send information to memory
controllers that consequently increases fan speed to regulate the temperature. The internal registers of
the processor are protected by ECC. Additionally there is a redundancy clocks and soft error hardened
latches and registers to improve resistance to soft errors.
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