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18 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE Single Event Transient (SET) An SET is a transient pulse in the logic path of an IC. Similar to an SEU, it is induced by a charge deposition of a single ionizing particle. An SET can be propagated along the logical path where it was created. It may be latched into a register, latch or flip-flop causing their output value to change. Single Event Functional Interrupt (SEFI) Xilinx [BCT08] defines SEFI as an SEE that results in the interference of the normal operation of a complex digital circuit. As for the previously mentioned SETs, further investigation of SEFI rates are not considered for this thesis. Single Event Latch-Up (SELU) A spurious current spike induced by an ionizing particle in a transistors may be amplified by the large positive feedback of the thyristor and cause a virtual short between Vdd and ground, resulting into a s SELU [NTN + 09]. SELUs are not addressed in this thesis. Single Event Gate Rupture (SEGR) and Single Event Burnout (SEB) Single Event Gate Rupture (SEGR) is a single ion induced condition in power MOSFETs that may result in the formation of a conducting path in the gate oxide. Single Event Burnout is a condition, which can cause device destruction due to a high current state in a power transistor. Both of them are permanent faults and not addressed in this thesis. 1.2 Basic Concepts and Taxonomy of <strong>Dependable</strong> Computing This part defines the basic terminologies related to dependable computing. The terminologies are globally extracted from [LB07, Lap04]. In this section, we identify the important methods and their characteristics to make a system tolerant to faults. 1.2.1 Dependability Dependability is the ability to deliver service that can justifiably be trusted [LRL04]. The defini- tion is focused on trust. In other words, the dependability of a system is the ability to avoid service failures that are more frequent and more severe than acceptable. Dependability relies on a set of measures that allow all phases of product life, to ensure that the functionality will be maintained while accomplishing the mission for which it has been designed. According to Laprie [LB07], the dependability of a system is the property that places a justified confidence in the service it delivers.
1.3. ATTRIBUTES 19 Dependability and Security 1.3 Attributes Attributes Threats Means Dependability Security Figure 1.4: Dependability Tree Availability Reliability Safety Confidentiality Integrity Maintainability Faults Errors Failure Fault Prevention Fault Tolerance Fault Removal Fault Forecasting Dependability is a vast concept based on various attributes as shown in figure 1.4. • Availability: it is the readiness for correct service; • Reliability: it is the continuity of correct service; • Safety: it is the absence of the catastrophic consequences on the user(s) and the environment; • Integrity: it is the absence of the improper system alterations; • Maintainability: it is the ability to undergo modifications. Moreover, when dealing with the security issues, an additional attribute called confidentiality is also considered as shown in figure 1.4. Confidentiality is the absence of unauthorized disclosure of information. Some other attributes related to security are availability and integrity, which have already been discussed with dependability attributes [VK07]. It is difficult to fully respect all of the dependability attributes at a time in a system because it can increase the cost, power consumption and hardware area of the system. So, one respects these attributes according to the system needs. It has been stated in [FGAM10] that it is impossible to design a 100% dependable system. For example, in-order to improve the availability of component,
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3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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