Theoretical and Experimental DNA Computation (Natural ...

1
0
1
1
g 1
g
2
1 2
(a)
(b)
g 3
g 1
g 2
g 3
?
(c)
g 1
g 2
g 2 chopped
Retain g 1 and snip off output section
g 3
g 3 retained, therefore circuit has output value = 1
4.7 Analysis 87
Level 1
Level 2
Fig. 4.6. (a) Circuit to be simulated. (b) Strand representing gates. (c) Stages of
the simulation
4.7 Analysis
We now compare both our and Ogihara and Ray’s models by describing how
Batcher sorting networks [22] may be implemented within them. Batcher networks
sort n inputs in O(log 2 n) stages. In [157], Wegener showed that if n =2 k
then the number of comparison modules is 0.5n(log n)(log n−1)+2n−2. The
circuit depth (again expressed in terms of the number of comparison modules)
is 0.5(log n)(log n+1). A comparison module has two (Boolean) inputs, x and
y, and two outputs, MIN(x, y) (whichisjustxANDy)andMAX(x, y)
(which is just xORy).
Using NAND we can build a comparison module with five NAND gates
and having depth 2 (the module is levelled; so since the Batcher network is
levelled with respect to comparison modules, the whole realization in NAND
gates will be levelled). The NAND gate realization is
MIN(x, y) =NAND(NAND(x, y),NAND(x, y)) - 2 gates, depth 2;
MAX(x, y) =NAND(NAND(x, x),NAND(y, y)) - 3 gates, depth 2;
If we assume that n =2 k we get the total size (in terms of number of gates)
as 2.5(log n)(log n − 1) + 10n − 10 and depth (in gates) as (log n)(logn +1).
Ogihara and Ray use an AND and OR gate simulation, so they would realize
a comparison module with two gates (MAX(x, y) =xORy; MIN(x, y) =