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Theoretical and Experimental DNA Computation (Natural ...

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4.9 P-RAM Simulation 91<br />

algorithm may be emulated in <strong>DNA</strong>. The P-RAM is a widely used model in the<br />

design of efficient parallel algorithms, especially by the international community<br />

of theorists working in the field. There are literally thous<strong>and</strong>s of published<br />

algorithms within this model which, often employing ingenious combinatorics,<br />

are remarkably efficient. One of the attractions of our approach is that we can<br />

call upon this vast published expertise. The immediate difficulty however is<br />

that it is not clear how to directly emulate the P-RAM in <strong>DNA</strong> without invoking<br />

great intricacy <strong>and</strong> unrealistic bench chemistry. On the other h<strong>and</strong>, we<br />

have been able to describe how a Boolean circuit may be efficiently emulated<br />

in <strong>DNA</strong>. Although both models are universal (that is, are Turing-complete),<br />

it is in general very difficult to “program” a Boolean circuit (that is, to design<br />

such a circuit to solve a specific problem) without a great degree of low<br />

level intricacy <strong>and</strong> opacity. The reverse is true for the P-RAM which yields<br />

a natural, high-level, programming environment. The benefit of our methodology<br />

is that we are able to describe a general method for compiling P-RAM<br />

algorithms into Boolean Combinational Logic Networks.<br />

Overall, then, we believe that we have a theoretical model which is easy<br />

to program, may call upon a vast literature of efficient parallel algorithmic<br />

design, <strong>and</strong> which (through Boolean circuit emulation) has the prospect of<br />

emulation in <strong>DNA</strong> using relatively simple <strong>and</strong> clean processes. Moreover, <strong>and</strong><br />

very importantly, there is only a logarithmic loss in efficiency in the emulation<br />

process. We now outline, in greater technical detail, how the emulation works.<br />

The work presented in [8] gives a simulation of Boolean networks by <strong>DNA</strong><br />

algorithms that requires parallel time comparable to the network depth <strong>and</strong><br />

volume comparable to the network size. This follows the work of Ogihara <strong>and</strong><br />

Ray [113], in which they describe a Boolean circuit model that, within our<br />

strong model of <strong>DNA</strong> computation [10], runs in parallel time proportionate<br />

to the circuit size. Although we point out in [8] that a simple modification<br />

to Ogihara <strong>and</strong> Ray’s simulation would achieve the same time complexity of<br />

our simulation, we believe that the biological implementation of our model is<br />

more straight forward. We justify this remark later.<br />

The crucial extension of our simulation is presented in [9]: this presents<br />

a full detailed translation from the high-level P-RAM algorithms into <strong>DNA</strong>,<br />

the translation being accomplished by using a Boolean network representation<br />

of the P-RAM algorithm as an intermediate stage. In total this translation<br />

achieves the following performance: if A is a P-RAM algorithm using P (n)<br />

processors, taking S(n) memory space, <strong>and</strong> taking T (n) time, then the total<br />

computation time of the <strong>DNA</strong> algorithm is bounded by O(T (n)logS(n)),<br />

<strong>and</strong> the total volume of <strong>DNA</strong> used is O(P (n)T (n)S(n)logS(n)). As a consequence<br />

this gives a direct translation from any NC algorithm into an effective<br />

<strong>DNA</strong> algorithm. The simulation presented thereby moves the purely theoretical<br />

“in principle” result that <strong>DNA</strong> can realize NC “efficiently” into the<br />

realm where such algorithms can be realized in <strong>DNA</strong> by a practical, universal<br />

translation process. In [9] a formal definition of the low-level instruction set<br />

available to each processor in the P-RAM is specified: this provides st<strong>and</strong>ard

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