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Theoretical and Experimental DNA Computation (Natural ...

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4.10 The Translation Process 97<br />

block Bk−1(i) correspond to the contents of memory location M[i] priorto<br />

the execution of Ik by SA; Ck produces as its output r × S(n) Boolean values<br />

arranged as S(n) r-bit blocks, the values in the i th block Bk(i) corresponding<br />

to the contents of memory location M[i] after the execution of Ik by SA.<br />

As a consequence of the translation just described, the programs corresponding<br />

to the actions of each processor working in parallel at some stage<br />

of the computation consist of identical (except for memory references) linear<br />

control graphs. A typical linear graph consists of processing some values<br />

stored in memory (using the accumulator), storing a value computed in memory,<br />

<strong>and</strong> repeating this sequence until its computation is completed. We can<br />

thus simulate this process by building a circuit which consists of several levels<br />

–each level mimics the calculations performed in the program <strong>and</strong> ends with<br />

either a halt instruction or a store instruction. What has to be ensured in the<br />

circuit simulation is that the store <strong>and</strong> halt instructions have an effect only if<br />

their controlling conditions evaluate to true. Thus, let L =< l1,l2,...,lt > be<br />

a sequence of instructions such that lt has the form < conditional > HALT ,<br />

< conditional > ST A, or< conditional > ST I, <strong>and</strong>lk(1 ≤ k

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