Theoretical and Experimental DNA Computation (Natural ...

92 4 Complexity Issues
memory access facilities (load and store), basic arithmetic operations, and
conditional branching instructions. The compilation into DNA involves three
basic stages: compiling the P-RAM program down to a low-level sequence
of instructions; translating this program into a combinational logic network;
and, finally, encoding the actions of the resulting Boolean networks into DNA.
The actions performed in the second stage lie at the core of the translation.
For each processor invoked at the kth parallel step, there will be identical
(except for memory references) sequences of low-level instructions; the combinational
logic block that simulates this (parallel) instruction takes as its input
all of the bits corresponding to the current state of the memory, and produces
as output the same number of bits representing the memory contents after
execution has completed. Effecting the necessary changes involves no more
than employing the required combinational logic network to simulate the action
of any low-level instruction. The main overhead in the simulation comes
from accessing a specific memory location, leading to the logS(n) slow-down.
All other operations can be simulated by well established combinational logic
methods without any loss in runtime. It is well known that the NAND function
provides a complete basis for computation by itself; therefore we restrict
our model to the simulation of such gates. In fact, the realization in DNA of
this basis provides a far less complicated simulation than using other complete
bases.
We now describe the simulation in detail. This detailed work is due mainly
to the second author of [9], and is used with permission. We provide a full,
formal definition of the CREW P-RAM model that we will use. This description
will consider processors, memory, the control regime, memory access
rules, and the processor instruction set. Finally we describe the complexity
measures that are of interest within this model.
The p processors, labelled P1,P2,...,Pp are identical, and can execute instructions
from the set described below. Processors have a unique identifier:
that of Pi being i. The global common memory, M, consists of t locations
M1,M2,...,Mt, each of which is exactly r-bits long. The initial input data
consists of n items, which are assumed to be stored in locations M[1],...,M[n]
of the global memory. The main control program, C, sequentially executes instructions
of the form
k; for x ∈ Lk par do instk(x)
Lk is a set of processor identifiers. For each processor Px in this list the instruction
specified by instx is executed. Each processor executes the same sequence
of instructions, but on different memory locations. The control program language
augments the basic parallel operation command with the additional
control flow statements
for counter-name ← start-value step step-value to end-value do
instruction-sequence