Medical Applications User Guide (pdf) - Freescale Semiconductor

Diagnostic and Therapy Devices
Key Features
• ARM Cortex-M4 core + DSP. 120-150 MHz,
single cycle MAC, single instruction multiple
data (SIMD) extensions, single precision
floating point unit
• 512 KB-1 MB flash. Fast access, high
reliability with four-level security protection
• Up to four high-speed 16-bit analog-todigital
converter (ADC) with configurable
resolution. Single or differential output mode
operation for improved noise rejection.
500 ns conversion time achievable with
programmable delay block triggering
• System security and tamper detect with
secure real-time clock with independent
battery supply. Secure key storage with
internal/external tamper detect for unsecure
flash, temperature, clock, and supply
voltage variations and physical attack
detection
PXS20 Family of 32-bit Power
Architecture MCUs
The PXS20 targets industrial applications
which require compliance with IEC61508
(SIL 3) safety standard. It reduces design
complexity and component count by putting
key functional safety features on a single chip
with a dual-core, dual-issue architecture,
which can be statically switched between
lockstep mode (redundant processing and
calculations) to decoupled parallel mode
(independent core operation). The PXS20
MCUs are SafeAssure functional safety
solutions.
Key Features
• Dual e200z4 CPU architecture
• Dual processing spheres including: CPU,
DMA, interrupt controller, crossbar and
MPU for logic level fault detection
• Two statically configurable modes of
operation: Lockstep operation (redundant
processing and calculations) and Dual
Parallel Mode (independent core operation)
• Fault Collection Unit, which monitors and
manages fault events
• Error correction coding on RAM and flash
memory allows detection/correction of
memory errors
Figure 12-3: 13-3: Kinetis K60 K60 Family Family Block Block Diagram Diagram
Figure 12-3: Kinetis K60 Family Block Diagram
Core
System Memories
Clocks
Internal and
ARM External
Watchdogs
Debug
Memory
DSP
Interfaces
Protection Unit
(MPU)
Interrupt Floating Point
Controller Unit (FPU)
DMA
Low-Leakage
Wake-Up Unit
Security Analog Timers
and Integrity
Cyclic
Redundancy
Carrier
Check (CRC)
Modulator
Transmitter
Random
Number
Generator
Cryptographic
Periodic
Acceleration
Interrupt
Unit (CAU)
Timers
H/W Tamper
Detection
Unit
Independent
Phase-Locked
Loop
Frequency-
Locked Loop
Low/High-
Frequency
Oscillators
Internal
Reference
Clocks
Communication Interfaces HMI
Xtrinsic
Low-Power
Touch-Sensing
Interface
Real-Time
Clock (RTC)
® Cortex-M4
100/120/150 MHz
16-bit
ADC
FlexTimer
PGA
Analog
Comparator Programmable
Delay Block
6-bit
DAC
12-bit
DAC
Low-Power
Timer
Voltage
Reference
IEEE ® Program Flash SRAM
(256 KB to 1 MB) (64 to 128 KB)
FlexMemory External
(256 to 512 KB) Bus Interface
(4 to 16 KB EE) (FlexBus)
Serial
Cache
Programming
Interface
(EzPort) DDR Controller
NAND Flash
Controller
I GPIO
1588
Timer
2C I
UART
(ISO 7816)
SPI
CAN
IEEE 1588
Ethernet MAC
2 Core
System Memories
Clocks
Internal and
ARM External
Watchdogs
Debug
Memory
DSP
Interfaces
Protection Unit
(MPU)
Interrupt Floating Point
Controller Unit (FPU)
DMA
Low-Leakage
Wake-Up Unit
Security Analog Timers
and Integrity
Cyclic
Redundancy
Carrier
Check (CRC)
Modulator
Transmitter
Random
Number
Generator
Cryptographic
Periodic
Acceleration
Interrupt
Unit (CAU)
Timers
H/W Tamper
Detection
Unit
Independent
Real-Time
Clock (RTC)
Standard Feature
Phase-Locked
Loop
Frequency-
Locked Loop
Low/High-
Frequency
Oscillators
Internal
Reference
Clocks
Communication Interfaces HMI
Xtrinsic
Low-Power
Touch-Sensing
S Interface
Secure
Digital Host
Controller
(SDHC)
USB On-the-Go
(LS/FS)
USB On-the-Go
(HS)
USB Device
Charger Detect
(DCD)
USB Voltage
Regulator
® Cortex-M4
100/120/150 MHz
16-bit
ADC
FlexTimer
PGA
Analog
Comparator Programmable
Delay Block
6-bit
DAC
12-bit
DAC
Low-Power
Timer
Voltage
Reference
IEEE ® 1588
Timer
Program Flash SRAM
(256 KB to 1 MB) (64 to 128 KB)
FlexMemory External
(256 to 512 KB) Bus Interface
(4 to 16 KB EE) (FlexBus)
Serial
Cache
Programming
Interface
(EzPort) DDR Controller
NAND Flash
Controller
I GPIO
2C I
UART
(ISO 7816)
SPI
CAN
IEEE 1588
Ethernet MAC
2 Optional Feature
S
Secure
Digital Host
Controller
(SDHC)
USB On-the-Go
(LS/FS)
USB On-the-Go
(HS)
USB Device
Charger Detect
(DCD)
USB Voltage
Regulator
Figure 12-4: PXS20 Family Block Diagram
Figure 12-4: 13-4: PXS20 PXS20 Family Family Block Block Diagram Diagram
Standard Feature Optional Feature
Core
Core
System
System
Debug
System
System
Core
Core
Frequency
Frequency Modulated PLL
JTAG
JTAG
Nexus
Frequency
Modulated Frequency PLL
e200z4
e200z4
Modulated Software PLL
Watchdog
Software
System
Watchdog Timer
Nexus
System
Boot Assist
Module System (BAM)
Software Modulated PLL
Watchdog
Software
System
Timer Watchdog
e200z4
e200z4
FPU System Interrupt
Controller
Timer
Boot Clock Monitor Assist
Unit
Module (BAM)
Interrupt System
Controller
Timer
FPU
FPU
VLE
VLE
CACHE
MMU
DMA
Interrupt (up to 32-ch.)
Controller
Crossbar
Switch
DMA
(up to 32-ch.) Memory
Protection Unit
Semaphone
Clock Unit Monitor
Unit
VReg
Semaphone
4 x Redundancy Unit
Checker
DMA
(up to 32-ch.) Interrupt
Controller
Crossbar
Switch
DMA
Memory (up to 32-ch.)
Protection Unit
VLE
CACHE
MMU
FPU
VLE
CACHE
Crossbar
Memory Switch
Control
VReg
Crossbar
Switch Communication
CACHE
MMU
3 x
2 x
Memory Timer 4 (6-ch.) x Redundancy Fault Control Memory
Up MMU
Protection to 1 MB
UART
Unit Checker and Protection Unit
Flash
3 x
Collection Unit
3 x
w/ECC
PWM (4-ch.)
SPI
Memory
Up to 4 ADC Control
Communication
2 x
Up to 128 KB
(34-ch.)
Cyclic
CAN
3 x
Redundancy
2 x
SRAM
Timer Cross (6-ch.) Trigger Fault Checker Control External
Up to 1 MBw/ECC
UART
Unit
and
Bus
(32 KB S/B)
Flash
3 Periodic x
Collection Sine Wave Unit
3 x
w/ECC
PWM Interrupt (4-ch.) Timer Generator
SPI
Up to 128 KB
SRAM
w/ECC
(32 KB S/B)
Temperature
Up to Sensor 4 ADC
(34-ch.)
Cross Trigger
Unit
Cyclic
Redundancy
Checker
2 x
CAN
External
Bus
Periodic
Interrupt Timer
Temperature
Sine Wave
Generator
• Designed to address safety requirements
Sensor
outlined in IEC61511 and IEC61508 (SIL3)
• Robust communications CAN/safety port
high speed low latency messaging
• Cross-triggering unit coordinates ADC,
timer and PWM generation and minimizes
CPU interrupt load
• Integrated timer and analog peripherals
support precise control of integrated
electric motor control periphery, enables
the device to control of up to two brushless
3-phase motors or multiple valves with only
minimum interrupt load
74 Medical Applications User Guide