THE OCULUS-F/64 FRAME GRABBER User's Manual

1.8 MEMORY
The Oculus-F/64 incorporates a high speed digital signal processor and graphic
signal processor, both of which operate in conjunction with a real-time
histogram processor and Coreco's proprietary “Image Processing Engine” (IP-
Engine). These elements, combined with a high memory communications
bandwidth, (80 Mbytes/sec on the VRAM bus plus 40 Mbytes/sec on the
DRAM [DSP] bus for a total of 120 Mbytes/sec), provide enough processing
throughput for any imaging application. The following table lists performance
specifications for a standard RS-170 camera with 512 x 512 images.
Function Performed By Time
Histogram Histogram Processor Frame Time
Addition IP-Engine Frame Time
Subtraction IP-Engine Frame Time
Division DSP TBA
Convolution
(Laplacian)
DSP TBA
2D FFT DSP TBA
The Oculus-F/64 uses VRAM memory to image display and both DRAM and
VRAM memory for image acquisition and processing. Physical frame buffer
arrays can be programmed into smaller logical frame buffers enabling
acquisition and processing of multiple images.
1.8.1 FIELD UPGRADEABLE MEMORY MODULES
Field upgradeable VRAM memory modules, available in sizes of 2, 4, or 8
Mbytes, simplify memory expansion. Oculus-F/64 products can accommodate
up to 16 Mbytes of VRAM memory and 32 Mbytes of DSP DRAM memory,
and 32 Mbytes GSP DRAM memory for a total of 80 Mbytes of on board
memory.
1.8.2 PROGRAM AND OVERLAY MEMORY
Oculus-F/64 products accommodate up to 4 Mbytes of graphic and text overlay
memory. TMS34020 GSP program code is stored in on-board DRAM
memory, expandable to a maximum of 32 megabytes. GSP memory can also
be used to store and process image data. TMS320C40 DSP program code is
stored in 128 kbyte of 0 wait-state SRAM memory while operating on DRAM
memory frame buffer which can be expanded to a maximum of 32 Mbytes.
1.8.3 16 BIT FRAME BUFFER
Coreco Inc., General Overview Page 1-5