THE OCULUS-F/64 FRAME GRABBER User's Manual

3.3 PROCESSING
From
Acquisition
Section
8/16 Bit
Data
Coreco
F/64 Bus
Coreco
IP-Engine
Feedback
8/16 Bit, 40 Mbyte/sec
DRAM Frame
Buffer
1-32 Mbytes
6 Channels, 8 Bits each
20 Mbytes/sec
16 Bit
3.3.1 IP ENGINE
10 Bit
MUX /
DEMUX
8/16 to 32
Bus
Arbitrator
Histogram
Processor
TMS320C40
40 MHz DSP
(optional)
80 Mbyte/sec
To 16 Bit ISA Bus
TMS34020
40 MHz GSP
TMS34094
Host
Interface
VRAM Frame
Buffer
1-16 Mbytes
To Display
Section
4 Channels,
8 Bits each
To Overlay
LUT
Coreco Inc., The OCULUS-F/64 Block Diagram Page 3-7
32 Bits
GSP DRAM
1 to 32 Mbytes
Overlay
Frame
Buffer
Coreco's proprietary IP-Engine performs real-time image averaging,
subtractions, and logical operations. The IP-Engine is a 40 MIP processor
which performs mathematical operations between incoming images and images
already stored in a selected frame buffer. The flexibility of the IP-Engine
allows it to be factory programmed with custom functions, for real-time
execution of repetitive operations.
3.3.2 HISTOGRAM PROCESSOR
The Oculus-F/64 series incorporates a real-time histogram processor which
produces histograms on images ranging in size up to 4k by 4k. Real-time
histograms facilitate object identification, object detection and intensity
analysis. The histogram processor operates independently of any other
processor, with input data (8 or 10 bit only) read from the IP-Engine output
bus. The histogram processor result data is read directly by the GSP, allowing
for display of that data or transfer to the on-board DSP or host system
application.
3.3.3 TMS34020 GRAPHIC SIGNAL PROCESSOR
The TMS34020 GSP advanced 32 bit processor is standard on all Oculus-F/64
boards. This high performance 40 MHz processor is optimized for imaging
and graphics applications because of its unique array addressing support and
efficient manipulation of hardware-supported data types such as pixels and
2-dimensional pixel arrays. The GSP architecture provides for high
performance in moving large blocks of data, data management, display control
and refresh, image processing, and host communications. The TMS34020 is
also responsible for all operations within the graphics overlay plane.