mitac 8355.pdf - tim.id.au

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8355 N/B MAINTENANCE 4. Definition & Location of Major Components 4.1 Main Board (Side B) PU502 U503 U506 U523 U509 U511 U517 U518 U514 U516 U503 : CPU Socket U506 : North Bridge VT8385 U509 : PC87393 Super I/O Controller U511 : H8/F3437 Micro Controller U514 : ENE CP710 PCMCIA &Reader Controller U516 : VT6307L IEEE1394 Controller U517 :TPA0202 Audio Amplifier U518 : CMI9738 Audio CODEC U523 : On Board External VRAM PU502 :CPU Power Controller 99
DDR SDRAM Memory Interface Signal Name Type Description MEMCLK_H/L[7] O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for unbuffered DIMMs. 1 MEMCLK_H/L[6] O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for unbuffered DIMMs. 1 MEMCLK_H/L[5] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for unbuffered DIMMs. 1 MEMCLK_H/L[4] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for unbuffered DIMMs. 1 MEMCLK_H/L[3] O-IOD Differential DDR SDRAM clock to DIMM 3 for registered DIMMs. 1 MEMCLK_H/L[2] O-IOD Differential DDR SDRAM clock to DIMM 3 for registered DIMMs. 1 MEMCLK_H/L[1] O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for unbuffered DIMMs, or DIMM 1 for registered DIMMs. 1 MEMCLK_H/L[0] O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for unbuffered DIMMs, or DIMM 1 for registered DIMMs. 1 MEMCKEA O-IOS Clock Enables to DIMMs. Used to gate clocks for power MEMCKEB management functionality. 1 MEMDQS[17:0] B-IOS DRAM Data Strobes synchronous with MEMDATA and MEMCHECK during DRAM read and writes. 1 MEMDATA[63:0] B-IOS DRAM Interface Data Bus MEMCHECK[7:0] B-IOS DRAM Interface ECC Check Bits MEMCS_L[7:0] O-IOS DRAM Chip Selects 1 MEMRASA_L MEMRASB_L MEMCASA_L MEMCASB_L MEMWEA_L MEMWEB_L MEMADDA[13:0] MEMADDB[13:0] O-IOS O-IOS O-IOS O-IOS 8355 N/B MAINTENANCE 5. Pin Descriptions of Major Components 5.1 AMD ATHLON TM 64 Processor-1 DRAM Row Address Select. MEMRASA_L and MEMRASB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs. 1 DRAM Column Address Select. MEMCASA_L and MEMCASB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs.1 DRAM Write Enable. MEMWEA_L and MEMWEB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs. 1 DRAM Column/Row Address. Two copies are provided to accommodate the loading of unbuffered DIMMs. During precharges, activates, reads, and writes, the two copies are inverted from each other (except A[10] which is used for auto-precharge) to minimize switching noise. The signals are inverted only when the bus is used to carry address information. 1 DDR SDRAM Memory Interface Continue Signal Name Type Description MEMBANKA[1:0] MEMBANKB[1:0] O-IOS DRAM Bank Address. Two copies are provided to accommodate the loading of unbuffered DIMMs. During precharges, activates, reads, and writes the two copies are inverted from each other to minimize switching noise. The signals are inverted only when the bus is used to carry address information. 1 MEMRESET_L O-IOS DRAM Reset pin for Suspend-to-RAM power management mode. This pin is required for registered DIMMs only. MEMVREF VREF DRAM Interface Voltage Reference 1 MEMZP A Compensation Resistor tied to VSS 1 MEMZN A Compensation Resistor tied to 2.5 V 1 Notes: 1. For connection details and proper resistor values, see the AMD Athlon 64 Processor Motherboard Design Guide, order# 24665. JTAG Pin Descriptions Signal Name Type Description TCK I-IOS JTAG Clock TMS I-IOS JTAG Mode Select TRST_L I-IOS JTAG Reset TDI I-IOS JTAG Data Input TDO O-IOS JTAG Data Output Clock Signal Name Type Description CLKIN_H/L I-IOD 200-MHz PLL Reference Clock FBCLKOUT_H/L O-IOD Core Clock PLL 200-MHz Feedback Clock 100
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SERVICE SERVICE MANUAL MANUAL FOR F
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Contents 8355 N/B MAINTENANCE 5.3 V
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1.1 Introduction 8355 N/B MAINTENAN
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1.2 System Hardware Part 8355 N/B M
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8355 N/B MAINTENANCE HyperTransport
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1.2.2 System frequency 8355 N/B MAI
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1.2.3 VIA K8T800+VT8235 1.2.3.1 K8T
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LRU replacement scheme 8355 N/B MAI
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8355 N/B MAINTENANCE f) Notebook-cl
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8355 N/B MAINTENANCE SMOOTHVISION
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1.2.4.1 General and Interfacing Fea
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8355 N/B MAINTENANCE DDC1 and DDC2c
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+30dB boost preamplifier for MIC in
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Operating System Compatibility Wind
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8355 N/B MAINTENANCE 1200/75bps (V.
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Transmit Level >-15 dBm 8355 N/B MA
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Arbitrated short reset Enhanced pri
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Instruction length: 2 or 4 bytes 83
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Interrupts - 8355 N/B MAINTENANCE 9
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1.2.9 System Flash Memory (BIOS) 2
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Dual Speed - 100 / 10 Mbps Half and
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Secure Digital Interface 8355 N/B M
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Supports SUSPEND# Supports PCI PME#
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PPM for external FDD signal support
Page 49 and 50: 8355 N/B MAINTENANCE 1.3.2 Power ON
Page 51 and 52: 1.3.6 CMOS Battery CR2032 3V 220mAh
Page 53 and 54: 1.4 Peripheral Components ROM Drive
Page 55 and 56: HDD: spin down Suspend to DRAM 8355
Page 57 and 58: 8355 N/B MAINTENANCE 1.6 Appendix 1
Page 59 and 60: 1.7 Appendix 2: H8 Pins Definition
Page 61 and 62: Continued to the previous table Por
Page 63 and 64: Continued to the previous table Por
Page 65 and 66: Continued to the previous table Ind
Page 67 and 68: 2. System View and Disassembly 2.1
Page 69 and 70: 2.1.5 Bottom View 1 2 CPU Cover Har
Page 71 and 72: NOTEBOOK 8355 N/B MAINTENANCE Modul
Page 73 and 74: 2.2.2 Keyboard Disassembly 8355 N/B
Page 75 and 76: 8355 N/B MAINTENANCE 5. Disconnect
Page 77 and 78: 8355 N/B MAINTENANCE 5. Disconnect
Page 79 and 80: 8355 N/B MAINTENANCE 5. Unscrew two
Page 81 and 82: 2.2.6 SO-DIMM Disassembly 8355 N/B
Page 83 and 84: 8355 N/B MAINTENANCE 6. Then remove
Page 85 and 86: 2.2.8 Inverter Board Disassembly 83
Page 87 and 88: 2.2.9 LCD Panel Disassembly 8355 N/
Page 89 and 90: 2.2.10 System Board Disassembly 835
Page 91 and 92: 8355 N/B MAINTENANCE 8. Unscrew one
Page 93 and 94: 2.2.11 Modem Card Disassembly Reass
Page 95 and 96: Reassembly 8355 N/B MAINTENANCE 1.
Page 97 and 98: 8355 N/B MAINTENANCE 3. Definition
Page 99: 8355 N/B MAINTENANCE 4. Definition
Page 103 and 104: 8355 N/B MAINTENANCE 5.2 K8T800M(VT
Page 105 and 106: AGP Bus Interface (Continued) Signa
Page 107 and 108: 5.3 VT8235 South Bridge-1 V-Link In
Page 109 and 110: 5.3 VT8235 South Bridge-3 PCI Bus I
Page 111 and 112: UltraDMA-133 /100 /66 /33 Enhanced
Page 113 and 114: Power Management and Event Detectio
Page 115 and 116: 5.3 VT8235 South Bridge-9 Power and
Page 117 and 118: 7. Maintenance Diagnostics 7.1 Intr
Page 119 and 120: 7.2 Error Codes Code 30h 31h 32h 33
Page 121 and 122: 7.3.2 Diagnostic Tool for PIO Port
Page 123 and 124: P30 Power In PJ501 PL1 PL2 PL3 PF1
Page 125 and 126: Power In +VMAIN_2951 F503 FUSE_1206
Page 127 and 128: P23 U511 H8/F3437 11 16 8355 N/B MA
Page 129 and 130: P2 P5 P7 P20 8.3 No Display U503 AM
Page 131 and 132: 8.3 No Display (System Failure) ALL
Page 133 and 134: U506 8355 N/B MAINTENANCE 8.4 AGP C
Page 135 and 136: 8.5 External Monitor No Display 835
Page 137 and 138: 8.6 Memory Test Error P2 8355 N/B M
Page 139 and 140: P22 U509 Super I/O PC87393 73 R216
Page 141 and 142: P13 8355 N/B MAINTENANCE 8.8 Hard D
Page 143 and 144: P13 1 2 8355 N/B MAINTENANCE 8.9 CD
Page 145 and 146: 8.10 USB Test Error (1) P12 8355 N/
Page 147 and 148: 8.10 USB Test Error USB Test Error
Page 149 and 150: 8.11 PC-Card Socket Failure PC Card
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8.12 Memory-Card Socket Failure Mem
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8.13 IEEE1394 Test Error 1394 Test
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8.14 LAN Test Error LAN Test Error
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P13 U20 South Bridge VT8235 8.15 Au
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9. Spare Part List-1 Part Number De
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9. Spare Part List-11 Part Number D
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9. Spare Part List-13 Part Number D
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5 COVER SHEET & SCREW HOLE ClawHamm
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5 5 1 2 4 4 ClawHammer-Power plane(
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1 2 1 2 5 5 1 2 1 2 GND 4 1 2 4 1 2
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5 5 4 4 ATI M10-P(1/4) 3 AGP_VDDQ +
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5 4 ATI M10-P(3/4) 3 D C MEMA_MD0 M
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+5V 5 CRTGND TV CONNECTOR 5 GND GND
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15 HD_PDD[0..15] 5 HD_PDD[0..15] 15
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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MINI-PCI AD21 PCI_INTD# REQ2#/GNT2#
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GND 5 GND R105 0603 1 2 0/NA 5 Q11
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5 5 4 4 AUDIO AMPLIFIER - TPA0202 3
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1 2 3 1 A K 1 2 1 2 1 2 5 1 2 1 2 1
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5 PCI PULL HIGH SB X-BUS PULL HIGH
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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5 5 4 4 FOR M10 +1.2V&+1.0V 3 D D 2
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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Reference Material AMD Athlon TM 6
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