mitac 8355.pdf - tim.id.au

5.3 VT8235 South Bridge-2
CPU Speed Control Interface
Signal Name Pin # I/O Signal Description
VGATE C8 I Voltage Gate. Signal from he CPU voltage regulator. High indicates
/GPIO8
he voltage regulator output is stable. This pin performs he VGATE
/PCREQA
function if Device 17 Function 0 Rx53[7]=0,E5[4]=1 and E4[3]=0.
VIDSEL P25 OD Voltage Regulator ID Select. Connected o he CPU voltage regulator.
/GPIO28
Low selects the voltage ID from the CPU; high selects a different
fixed voltage ID (the lower voltage used for CPU deep sleep mode).
This pin performs the VIDSEL function if Function 0 RxE5[3]=0.
VRDSLP P24 OD Voltage Regulator Deep Sleep. Connected to the CPU voltage
/GPIO29
regulator. High selects the proper voltage for deep sleep mode. This
pin performs he VRDPSLP function if Function 0 RxE5[3]=0.
GHI#/GPIO2 R24 OD CPU Speed Select. Connected o he CPU voltage regulator, used to
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select high speed (L) or low speed (H).This pin performs the GHI#
function if Function 0 RxE5[3]=0.
DPSLP#/GPI
O23
P26 OD CPU Deep Sleep.
CPUMISS Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in
/GPI17
its socket. High indicates no CPU present. Connect to the CPUMISS
pin of he CPU socket. The state of this pin may be read in the SMBus
2 registers. This pin may be used as CPUMISS and GPI17 at the same
time.
AGPBZ#/GPI A8 I AGP Busy. Low indicates that an AGP master cycle is in progress
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(CPU speed transitions will be postponed if his input is asserted
low).Connected to the AGP Bus AGPBZ# pin.
Summary of Internal Pull-Up /Pull-Down Resistor Implementation Internal Pullups are present on pins
KBCK,KBDT,MSCK,MSDT,SERIRQ,LAD [3:0 ]Internal Pulldowns are present on pins SA [19-16 ]
and all LAN pins
Low Pin Count (LPC)Interface
Signal Name Pin # I/O PU Signal Description
LFRM# AE7 IO LPC Frame.
LREQ# AD7 IO LPC DMA /Bus Master Request.
LAD[3-0] AF7,AD8,AE8, IO
AF8
PU LPC Address /Data.
Note: Connect the LPC interface LPCRST#(LPC Reset)signal to PCIRST#
8355 N/B MAINTENANCE
CPU Interface
Signal Name Pin # I/O Signal Description
A20M# T25 OD A20 Mask. Connect to A20 mask input of he CPU to control address
bi -20 generation. Logical combination of the A20GATE input (from
internal or external keyboard controller) and Port 92 bit -1 (Fast_A20).
FERR# U26 I Numerical Coprocessor Error. This signal is tied o he coprocessor
error signal on the CPU. Internally generates interrupt 13 if active.
Output voltage swing is programmable tot 1.5V or 2.5V by Device 17
Function 0 Rx67[2].
IGNNE# T26 OD Ignore Numeric Error. This pin is connected to the CPU “ignore
error”pin.
INIT# R25 OD Initialization. The VT8235 asserts INIT# if it detects a shut-down
special cycle on he PCI bus or if a soft reset is initiated by he register
INTR T23 OD CPU Interrupt. INTR is driven by he VT8235 to signal he CPU hat an
interrupt request is pending and needs service.
NMI R23 OD Non-Maskable Interrupt. NMI is used o force a non-maskable
interrupt to the CPU. The VT8235 generates an NMI when PCI bus
SERR# is asserted.
SLP# U25 OD Sleep. Used to put the CPU to sleep.
SMI# T24 OD System Management Interrupt. SMI# is asserted by he VT8235 o he
CPU in response to different Power-Management events.
STPCLK# R26 OD Stop Clock. STPCLK# is asserted by he VT8235 to the CPU to
throttle the processor clock.
Note: Connect each of the above signals to 150 .pullup resistors to VCC_CMOS (see Design Guide).
Serial EEPROM Interface
Signal Name Pin # I/O PU Signal Description
EECS# A13 O Serial EEPROM Chip Select.
EECK C14 O Serial EEPROM Clock.
EEDO A14 O Serial EEPROM Data Output.
EEDI B14 I Serial EEPROM Data Input.
These pins are disabled if the SDCS1#pin is strapped low to enable serial EEPROM connection via the
MII interface.
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