Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

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19.3.6.2 FIFO Interrupt Mode
In FIFO interrupt mode (the FIFO control register UARTi.UART_FCR[0] FIFO_EN bit is set to 1 and
relevant interrupts are enabled by the UARTi.UART_IER register), an interrupt signal informs the
processor of the status of the receiver and transmitter. These interrupts are raised when the RX/TX FIFO
threshold (the UARTi.UART_TLR[7:4] RX_FIFO_TRIG_DMA and UARTi.UART_TLR[3:0]
TX_FIFO_TRIG_DMA bit fields or the UARTi.UART_FCR[7:6] RX_FIFO_TRIG and
UARTi.UART_FCR[5:4] TX_FIFO_TRIG bit fields, respectively) is reached.
The interrupt signals instruct the MPU to transfer data to the destination (from the UART in receive mode
and/or from any source to the UART FIFO in transmit mode).
When UART flow control is enabled with interrupt capabilities, the UART flow control FIFO threshold (the
UARTi.UART_TCR[3:0] RX_FIFO_TRIG_HALT bit field) must be greater than or equal to the RX FIFO
threshold.
Figure 19-5 shows the generation of the RX FIFO interrupt request.
RX FIFO level
Programmable flow control threshold
Programmable FIFO threshold
Figure 19-5. RX FIFO Interrupt Request Generation
Zero byte
Interrupt request
MPU acknowledged interrupt request
and transferred enough bytes to
recover FIFO level below
threshold
Interrupt request active high
In receive mode, no interrupt is generated until the RX FIFO reaches its threshold. Once low, the interrupt
can be deasserted only when the MPU has handled enough bytes to put the FIFO level below threshold.
The flow control threshold is set at a higher value than the FIFO threshold.
Figure 19-6 shows the generation of the TX FIFO interrupt request.
3640 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
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