Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

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Integration www.ti.com 19.2 Integration This device contains 6 instantiations of the UART/IrDA (UARTIRDAOCP) peripheral. There are six UART modules called UART0 – UART5. UART0 provides wakeup capability. Only UART 1 provides full modem control signals. All UARTs support IrDA and CIR modes and RTS/CTS flow control (subject to pin muxing configuration). Figure 19-1 shows an example of system connectivity using UART communication with hardware handshake. L4 Peripheral Interconnect MPU Subsystem, PRU-ICSS, Wakeup Ctrl Interrupts PER_CLKOUTM2 (192 MHz) EDMA L4 Peripheral Interconnect MPU Subsystem, PRU-ICSS, Wakeup Ctrl Interrupts PER_CLKOUTM2 (192 MHz) EDMA Figure 19-1. UART/IrDA Module — UART Application PRCM /4 UART/IrDA/CIR Controller Register/FIFO Interface IRQ DMAREQ0 DMAREQ1 FCLK UART/IrDA/CIR Controller UART Pads UARTx_RXD UARTx_TXD UARTx_RTSn UARTx_CTSn UARTx_DTRn UARTx_DSRn UARTx_DCDn UARTx_RIN UART/Modem Figure 19-2 shows an example of system connectivity using infrared communication with remote control (consumer infrared). PRCM 19.2.1 UART Connectivity Attributes Figure 19-2. UART/IrDA Module — IrDA/CIR Application /4 Register/FIFO Interface IRQ DMAREQ0 DMAREQ1 FCLK UART Pads UARTx_IRTX UARTx_IRRX UARTx_SD UARTx_RCTX RX TX RTS CTS DTR DSR DCD RIN IrDA/CIR Transceiver RXD (IrDA) TXD SD/MODE RC (CIR) The general connectivity attributes for each of the UART modules are shown in Table 19-2 and Table 19- 3. Table 19-2. UART0 Connectivity Attributes Attributes Type Power Domain Wake-Up Domain Clock Domain PD_WKUP_L4_WKUP_GCLK (OCP) PD_WKUP_UART0_GFCLK (Func) 3628Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
www.ti.com Integration Table 19-2. UART0 Connectivity Attributes (continued) Attributes Type Reset Signals WKUP_DOM_RST_N Idle/Wakeup Signals Smart Idle / Wakeup Interrupt Requests 1 interrupt to MPU Subsystem (UART0INT), PRU-ICSS (nirq) and WakeM3 DMA Requests 2 DMA requests to EDMA (TX – UTXEVT0, RX – URXEVT0) Physical Address L4 Wakeup slave port Table 19-3. UART1–5 Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L4LS_GCLK (OCP) PD_PER_UART_GFCLK (Func) Reset Signals PER_DOM_RST_N Idle/Wakeup Signals Smart Idle Interrupt Requests UART1-2 1 interrupt per instance to MPU Subsystem (UART1INT, UART2INT) and PRU-ICSS (nirq) UART3-5 1 interrupt per instance to only MPU Subsystem (UART3INT, UART4INT, UART5INT) DMA Requests 2 DMA requests per instance to EDMA (TX – UTXEVTx, RX – URXEVTx) Physical Address L4 Peripheral slave port 19.2.2 UART Clock and Reset Management The UART modules use separate functional and bus interface clocks. Table 19-4. UART0 Clock Signals Clock Signal Max Freq Reference / Source Comments CLK Interface clock 100 MHz CORE_CLKOUTM4 / 2 pd_wkup_l4_wkup_gclk From PRCM FCLK Functional clock 48 MHz PER_CLKOUTM2 / 4 pd_wkup_uart0_gfclk from PRCM Table 19-5. UART1–5 Clock Signals Clock Signal Max Freq Reference / Source Comments CLK 100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk Interface clock From PRCM FCLK 48 MHz PER_CLKOUTM2 / 4 pd_per_uart_gfclk Functional clock From PRCM For UART operation, the functional clock is used to produce a baud rate up to 3.6M bits/s. Table 19-6 lists the supported baud rates, the requested divider, and the corresponding error versus the standard baud rate. SPRUH73E–October 2011–Revised May 2012 Universal Asynchronous Receiver/Transmitter (UART) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 3629
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