Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

Functional Description www.ti.com
On receive, the FIR receive state machine recovers the receive clock, removes the start flag, decodes the
4PPM incoming data, and determines frame boundary with a reception of the stop flag. It also checks for
errors such as an illegal symbol, a CRC error, and a frame-length error. At the end of a frame reception,
the LH reads the line status register (LSR) to find out possible errors of the received frame.
Data can be transferred both ways by the module but when the device is transmitting, the IR RX circuitry
is automatically disabled by hardware. See bit 5 in Section 19.5.1.26, Auxiliary Control Register, for a
description of the logical operation. Note: This applies to all three modes of SIR, MIR, and FIR.
19.3.8.2.4 IrDA Clock Generation: Baud Generator
The IrDA function contains a programmable baud generator and a set of fixed dividers that divide the 48-
MHz clock input down to the expected baud rate.
Figure 19-24 shows the baud rate generator and associated controls.
14 bits divisor:
1/(DLH,DLL)
DLH DLL
Figure 19-24. Baud Rate Generator
16x divisor (SIR)
41x,42x (MIR)
6x divisor
77x divisor (1.6 ms
on)
341x divisor (7.1 ms
off)
SIR
MIR
MDR1[2:0]
MODE_SELECT bit field
CAUTION
FIR
RXIR SIR/MIR
TXIR SIR/MIR
TXIR FIR
RXIR FIR
1.6/7.1 ms
SIP (MIR or FIR)
or
1.6 ms
pulse (SIR)
Before initializing or modifying clock parameter controls (UARTi.UART_DLH,
UARTi.UART_DLL), MODE_SELECT=DISABLE (UARTi.UART_MDR1[2:0])
must be set to 0x7). Failure to observe this rule can result in unpredictable
module behavior.
19.3.8.2.5 Choosing the Appropriate Divisor Value
Three divisor values are:
3664 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
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