Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

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Table 19-27. UART_EFR[3:0] Software Flow Control Options
Bit 3 Bit 2 Bit 1 Bit 0 TX, RX Software Flow Controls
0 0 X X No transmit flow control
1 0 X X Transmit XON1, XOFF1
0 1 X X Transmit XON2, XOFF2
1 1 X X Transmit XON1, XON2: XOFF1, XOFF2 (1)
X X 0 0 No receive flow control
X X 1 0 Receiver compares XON1, XOFF1
X X 0 1 Receiver compares XON2, XOFF2
X X 1 1 Receiver compares XON1, XON2: XOFF1, XOFF2 (1)
In these cases, the XON1 and XON2 characters or the XOFF1 and XOFF2 characters must be transmitted/received sequentially
with XON1/XOFF1 followed by XON2/XOFF2.
XON1 is defined in the UARTi.UART_XON1_ADDR1[7:0] XON_WORD1 bit field. XON2 is defined in the
UARTi.UART_XON2_ADDR2[7:0] XON_WORD2 bit field.
XOFF1 is defined in the UARTi.UART_XOFF1[7:0] XOFF_WORD1 bit field. XOFF2 is defined in the UARTi.UART_XOFF2[7:0]
XOFF_WORD2 bit field.
19.3.8.1.3.3.1 Receive (RX)
When software flow control operation is enabled, the UART compares incoming data with XOFF1/2
programmed characters (in certain cases, XOFF1 and XOFF2 must be received sequentially). When the
correct XOFF characters are received, transmission stops after transmission of the current character
completes. Detection of XOFF also sets the UARTi.UART_IIR[4] bit (if enabled by UARTi.UART_IER[5])
and causes the interrupt line to go low.
To resume transmission, an XON1/2 character must be received (in certain cases, XON1 and XON2 must
be received sequentially). When the correct XON characters are received, the UARTi.UART_IIR[4] bit is
cleared and the XOFF interrupt disappears.
NOTE: When a parity, framing, or break error occurs while receiving a software flow control
character, this character is treated as normal data and is written to the RX FIFO.
When XON-any and special character detect are disabled and software flow control is enabled, no valid
XON or XOFF characters are written to the RX FIFO. For example, when UARTi.UART_EFR[1:0] = 0x2, if
XON1 and XOFF1 characters are received, they are not written to the RX FIFO.
When pairs of software flow characters are programmed to be received sequentially
(UARTi.UART_EFR[1:0] = 0x3), the software flow characters are not written to the RX FIFO if they are
received sequentially. However, received XON1/XOFF1 characters must be written to the RX FIFO if the
subsequent character is not XON2/XOFF2.
19.3.8.1.3.3.2 Transmit (TX)
Two XOFF1 characters are transmitted when the RX FIFO passes the trigger level programmed by
UARTi.UART_TCR[3:0]. As soon as the RX FIFO reaches the trigger level programmed by
UARTi.UART_TCR[7:4], two XON1 characters are sent, so the data transfer recovers.
NOTE: If software flow control is disabled after an XOFF character is sent, the module transmits
XON characters automatically to enable normal transmission.
The transmission of XOFF(s)/XON(s) follows the same protocol as transmission of an ordinary byte from
the TX FIFO. This means that even if the word length is 5, 6, or 7 characters, the 5, 6, or 7 LSBs of
XOFF1/2 and XON1/2 are transmitted. The 5, 6, or 7 bits of a character are seldom transmitted, but this
function is included to maintain compatibility with earlier designs.
It is assumed that software flow control and hardware flow control are never enabled simultaneously.
3656 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
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