Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
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Functional Description www.ti.com<br />
Table <strong>19</strong>-20. <strong>UART</strong>/IrDA/CIR Register Access Mode Overview (continued)<br />
Address Registers<br />
Offset<br />
Configuration Mode A Configuration Mode B Operational Mode<br />
Read Write Read Write Read Write<br />
0x014 <strong>UART</strong>_LSR – <strong>UART</strong>_XON2_ADD <strong>UART</strong>_XON2_AD <strong>UART</strong>_LSR –<br />
R2 DR2<br />
0x018 <strong>UART</strong>_MSR <strong>UART</strong>_TCR (2)<br />
(1)<br />
/<strong>UART</strong>_TCR<br />
(2) (3)<br />
<strong>UART</strong>_TCR <strong>UART</strong>_TCR <strong>UART</strong>_MSR <strong>UART</strong>_TCR (2)<br />
(2) (3)<br />
/<strong>UART</strong>_XOFF1<br />
(2)<br />
/<strong>UART</strong>_XOFF1<br />
(1) (2)<br />
/<strong>UART</strong>_TCR<br />
0x01C <strong>UART</strong>_SPR <strong>UART</strong>_SPR <strong>UART</strong>_TLR <strong>UART</strong>_TLR <strong>UART</strong>_SPR <strong>UART</strong>_SPR<br />
(1)<br />
/<strong>UART</strong>_TLR<br />
(1) (2)<br />
/<strong>UART</strong>_TLR<br />
(2) (3)<br />
/<strong>UART</strong>_XOFF2<br />
(2)<br />
/<strong>UART</strong>_XOFF2<br />
(1) (2)<br />
/<strong>UART</strong>_TLR<br />
(1)<br />
/<strong>UART</strong>_TLR<br />
(2) (3) (2)<br />
0x020 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1<br />
0x024 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2<br />
0x028 <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL<br />
0x02C <strong>UART</strong>_RESUM <strong>UART</strong>_TXFLH <strong>UART</strong>_RESUME <strong>UART</strong>_TXFLH <strong>UART</strong>_RESUME <strong>UART</strong>_TXFLH<br />
E<br />
0x030 <strong>UART</strong>_SFREG <strong>UART</strong>_RXFLL <strong>UART</strong>_SFREGL <strong>UART</strong>_RXFLL <strong>UART</strong>_SFREGL <strong>UART</strong>_RXFLL<br />
L<br />
0x034 <strong>UART</strong>_SFREG <strong>UART</strong>_RXFLH <strong>UART</strong>_SFREGH <strong>UART</strong>_RXFLH <strong>UART</strong>_SFREGH <strong>UART</strong>_RXFLH<br />
H<br />
0x038 <strong>UART</strong>_UASR – <strong>UART</strong>_UASR – <strong>UART</strong>_BLR <strong>UART</strong>_BLR<br />
0x03C – – – – <strong>UART</strong>_ACREG <strong>UART</strong>_ACREG<br />
0x040 <strong>UART</strong>_SCR <strong>UART</strong>_SCR <strong>UART</strong>_SCR <strong>UART</strong>_SCR <strong>UART</strong>_SCR <strong>UART</strong>_SCR<br />
0x044 <strong>UART</strong>_SSR – <strong>UART</strong>_SSR – <strong>UART</strong>_SSR –<br />
0x048 – – – – <strong>UART</strong>_EBLR <strong>UART</strong>_EBLR<br />
0x050 <strong>UART</strong>_MVR – <strong>UART</strong>_MVR – <strong>UART</strong>_MVR –<br />
0x054 <strong>UART</strong>_SYSC <strong>UART</strong>_SYSC <strong>UART</strong>_SYSC <strong>UART</strong>_SYSC <strong>UART</strong>_SYSC <strong>UART</strong>_SYSC<br />
0x058 <strong>UART</strong>_SYSS – <strong>UART</strong>_SYSS – <strong>UART</strong>_SYSS –<br />
0x05C <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER<br />
0x060 <strong>UART</strong>_CFPS <strong>UART</strong>_CFPS <strong>UART</strong>_CFPS <strong>UART</strong>_CFPS <strong>UART</strong>_CFPS <strong>UART</strong>_CFPS<br />
0x064 <strong>UART</strong>_RXFIFO <strong>UART</strong>_RXFIFO_ <strong>UART</strong>_RXFIFO_LVL <strong>UART</strong>_RXFIFO_L <strong>UART</strong>_RXFIFO_LV <strong>UART</strong>_RXFIFO<br />
_LVL LVL VL L _LVL<br />
0x068 <strong>UART</strong>_TXFIFO <strong>UART</strong>_TXFIFO_ <strong>UART</strong>_TXFIFO_LVL <strong>UART</strong>_TXFIFO_L <strong>UART</strong>_TXFIFO_LV <strong>UART</strong>_TXFIFO<br />
_LVL LVL VL L _LVL<br />
0x06C <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2<br />
0x070 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2<br />
0x074 <strong>UART</strong>_FREQ_ <strong>UART</strong>_FREQ_S <strong>UART</strong>_FREQ_SEL <strong>UART</strong>_FREQ_SE <strong>UART</strong>_FREQ_SEL <strong>UART</strong>_FREQ_<br />
SEL EL L SEL<br />
0x080 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3<br />
0x084 <strong>UART</strong>_TX_DM <strong>UART</strong>_TX_DMA <strong>UART</strong>_TX_DMA_TH <strong>UART</strong>_TX_DMA_ <strong>UART</strong>_TX_DMA_T <strong>UART</strong>_TX_DM<br />
A_THRESHOL _THRESHOLD RESHOLD THRESHOLD HRESHOLD A_THRESHOL<br />
D D<br />
(1) MSR_SPR mode is active (see Section <strong>19</strong>.3.7.1.2, Register Access Submode)<br />
(2) TCR_TLR mode is active (see Section <strong>19</strong>.3.7.1.2, Register Access Submode)<br />
(3) XOFF mode is active (see Section <strong>19</strong>.3.7.1.2, Register Access Submode)<br />
<strong>19</strong>.3.7.2 <strong>UART</strong>/IrDA (SIR, MIR, FIR)/CIR Mode Selection<br />
To select a mode, set the <strong>UART</strong>i.<strong>UART</strong>_MDR1[2:0] MODESELECT bit field (see Table <strong>19</strong>-21).<br />
3648 <strong>Universal</strong> <strong>Asynchronous</strong> <strong>Receiver</strong>/<strong>Transmitter</strong> (<strong>UART</strong>) SPRUH73E–October 2011–Revised May 2012<br />
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