Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

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Functional Description www.ti.com 19.3 Functional Description 19.3.1 Block Diagram The UART/IrDA/CIR module can be divided into three main blocks: • FIFO management • Mode selection • Protocol formatting FIFO management is common to all functions and enables the transmission and reception of data from the host processor point of view. There are two modes: • Function mode: Routes the data to the chosen function (UART, IrDA, or CIR) and enables the mechanism corresponding to the chosen function • Register mode: Enables conditional access to registers For more information about mode configuration, see Section 19.3.7, Mode Selection. Protocol formatting has three subcategories: • Clock generation: The 48-MHz input clock generates all necessary clocks. • Data formatting: Each function uses its own state-machine that is responsible for the transition between FIFO data and frame data associated with it. • Interrupt management: Different interrupt types are generated depending on the chosen function: – UART mode interrupts: Seven interrupts prioritized in six different levels – IrDA mode interrupts: Eight interrupts. The interrupt line is activated when any interrupt is generated (there is no priority). – CIR mode interrupts: A subset of existing IrDA mode interrupts is used. In each mode, when an interrupt is generated, the UART_IIR register indicates the interrupt type. In parallel with these functional blocks, a power-saving strategy exists for each function. Figure 19-3 is the UART/IrDA/CIR block diagram. 3632 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
www.ti.com Functional Description L4 interconnect FIFO management FIFO Transmit interrupt generation FIFO Transmit FIFO Receive interrupt generation FIFO Transmit DMA request generation FIFO Receive UARTi_DMA_TX FIFO Transmit DMA request generation UARTi_DMA_RX 19.3.2 Clock Configuration Figure 19-3. UART/IrDA/CIR Functional Specification Block Diagram Mode selection UARTi.MDR1[2:0] MODESELECT Clock generation UART clock generation IrDA (SIR/MIR/ FIR) clock generation CIR clock generation DATA formatting UART mode UART data formatting IrDA mode SIR/MIR/FIR data formatting CIR mode CIR data formatting Interrupt management UART interrupt management IrDA interrupt management CIR interrupt management UARTi_IRQ UART pins IrDA pins CIR pins Each UART uses a 48-MHz functional clock for its logic and to generate external interface signals. Each UART uses an interface clock for register accesses. The PRCM module generates and controls all these clocks (for more information, see , Clock Domain Module Attributes, in Chapter 8, Power, Reset, and Clock Management). The idle and wake-up processes use a handshake protocol between the PRCM and the UART (for a description of the protocol, see , Module-Level Clock Managment, in Chapter 8, Power, Reset, and Clock Management). The UARTi.UART_SYSC[4:3] IDLEMODE bit field controls UART idle mode. 19.3.3 Software Reset The UARTi.UART_SYSC[1] SOFTRESET bit controls the software reset; setting this bit to 1 triggers a software reset functionally equivalent to hardware reset. 19.3.4 Power Management 19.3.4.1 UART Mode Power Management 19.3.4.1.1 Module Power Saving In UART modes, sleep mode is enabled by setting the UARTi.UART_IER[4] SLEEP_MODE bit to 1 (when the UARTi.UART_EFR[4] ENHANCED_EN bit is set to 1). Sleep mode is entered when all the following conditions exist: • The serial data input line, uarti_rx, is idle. • The TX FIFO and TX shift register are empty. • The RX FIFO is empty. • The only pending interrupts are THR interrupts. SPRUH73E–October 2011–Revised May 2012 Universal Asynchronous Receiver/Transmitter (UART) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated uart-022 3633
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