Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

Functional Description www.ti.com
1. Data to be transmitted are put in the device memory reserved for UART/IrDA/CIR transmission by the
DMA:
(a) Until the TX FIFO trigger level is not reached, a DMA request is generated
(b) An element (1 byte) is transferred from the SDRAM to the TX FIFO at each DMA request (DMA
element synchronization).
2. Data in the TX FIFO are automatically transmitted.
3. The end of the transmission is signaled by the UARTi.UART_THR empty (TX FIFO empty).
NOTE: In IrDA mode, the transmission does not end immediately after the TX FIFO empties, at
which point the last data byte, the CRC field, and the stop flag still must be transmitted; thus,
the end of transmission occurs a few milliseconds after the UARTi.UART_THR register
empties.
19.3.6.4.3 DMA Reception
Figure 19-13 shows DMA reception.
Received data
1. Enable the reception.
UART/
IrDA/CIR
RX FIFO
2. Received data are put in the RX FIFO.
Figure 19-13. DMA Reception
RX FIFO threshold
DMA request
DMA
3. Data are transferred from the RX FIFO to the device memory by the DMA:
Device
memory
Reserved for
IrDA
reception
(a) At each received byte, the RX FIFO trigger level (one character) is reached and a DMA request is
generated.
(b) An element (1 byte) is transferred from the RX FIFO to the SDRAM at each DMA request (DMA
element synchronization).
4. The end of the reception is signaled by the EOF interrupt.
19.3.7 Mode Selection
19.3.7.1 Register Access Modes
19.3.7.1.1 Operational Mode and Configuration Modes
Register access depends on the register access mode, although register access modes are not correlated
to functional mode selection. Three different modes are available:
• Operational mode
• Configuration mode A
• Configuration mode B
Operational mode is the selected mode when the function is active; serial data transfer can be performed
in this mode.
3646 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
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