Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
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Functional Description www.ti.com<br />
Table <strong>19</strong>-22. <strong>UART</strong> Mode Register Overview (1) (2) (continued)<br />
Address Registers<br />
Offset<br />
Configuration Mode A Configuration Mode B Operational Mode<br />
Read Write Read Write Read Write<br />
0x05C <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER <strong>UART</strong>_WER<br />
0x060 – – – – – –<br />
0x064 <strong>UART</strong>_RXFIFO <strong>UART</strong>_RXFIFO_ <strong>UART</strong>_RXFIFO_LVL <strong>UART</strong>_RXFIFO_L <strong>UART</strong>_RXFIFO_LV <strong>UART</strong>_RXFIFO<br />
_LVL LVL VL L _LVL<br />
0x068 <strong>UART</strong>_TXFIFO <strong>UART</strong>_TXFIFO_ <strong>UART</strong>_TXFIFO_LVL <strong>UART</strong>_TXFIFO_L <strong>UART</strong>_TXFIFO_LV <strong>UART</strong>_TXFIFO<br />
_LVL LVL VL L _LVL<br />
0x06C <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2 <strong>UART</strong>_IER2<br />
0x070 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2 <strong>UART</strong>_ISR2<br />
0x074 <strong>UART</strong>_FREQ_ <strong>UART</strong>_FREQ_S <strong>UART</strong>_FREQ_SEL <strong>UART</strong>_FREQ_SE <strong>UART</strong>_FREQ_SEL <strong>UART</strong>_FREQ_<br />
SEL EL L SEL<br />
0x080 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3 <strong>UART</strong>_MDR3<br />
0x084 <strong>UART</strong>_TX_DM <strong>UART</strong>_TX_DMA <strong>UART</strong>_TX_DMA_TH <strong>UART</strong>_TX_DMA_ <strong>UART</strong>_TX_DMA_T <strong>UART</strong>_TX_DM<br />
A_THRESHOL _THRESHOLD RESHOLD THRESHOLD HRESHOLD A_THRESHOL<br />
D D<br />
<strong>19</strong>.3.7.2.2 Registers Available for the IrDA Function<br />
Only the registers listed in Table <strong>19</strong>-23 are used for the IrDA function.<br />
(1) (2)<br />
Table <strong>19</strong>-23. IrDA Mode Register Overview<br />
Address Registers<br />
Offset<br />
Configuration Mode A Configuration Mode B Operational Mode<br />
Read Write Read Write Read Write<br />
0x000 <strong>UART</strong>_DLL <strong>UART</strong>_DLL <strong>UART</strong>_DLL <strong>UART</strong>_DLL <strong>UART</strong>_RHR <strong>UART</strong>_THR<br />
0x004 <strong>UART</strong>_DLH <strong>UART</strong>_DLH <strong>UART</strong>_DLH <strong>UART</strong>_DLH <strong>UART</strong>_IER(IrDA) <strong>UART</strong>_IER(IrD<br />
A)<br />
0x008 <strong>UART</strong>_IIR <strong>UART</strong>_FCR <strong>UART</strong>_EFR[4] <strong>UART</strong>_EFR[4] <strong>UART</strong>_IIR(IrDA) <strong>UART</strong>_FCR(Ir<br />
DA)<br />
0x00C <strong>UART</strong>_LCR[7] <strong>UART</strong>_LCR[7] <strong>UART</strong>_LCR[7] <strong>UART</strong>_LCR[7] <strong>UART</strong>_LCR[7] <strong>UART</strong>_LCR[7]<br />
0x010 – – <strong>UART</strong>_XON1_ADD <strong>UART</strong>_XON1_AD – –<br />
R1 DR1<br />
0x014 <strong>UART</strong>_LSR(IrD – <strong>UART</strong>_XON2_ADD <strong>UART</strong>_XON2_AD <strong>UART</strong>_LSR(IrDA) –<br />
A ) R2 DR2<br />
0x018 <strong>UART</strong>_MSR/U <strong>UART</strong>_TCR <strong>UART</strong>_TCR <strong>UART</strong>_TCR <strong>UART</strong>_MSR/<strong>UART</strong> <strong>UART</strong>_TCR<br />
ART_TCR _TCR<br />
0x01C <strong>UART</strong>_TLR/UA <strong>UART</strong>_TLR/UA <strong>UART</strong>_TLR <strong>UART</strong>_TLR <strong>UART</strong>_TLR/<strong>UART</strong>_ <strong>UART</strong>_TLR/UA<br />
RT_SPR RT_SPR SPR RT_SPR<br />
0x020 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1 <strong>UART</strong>_MDR1<br />
0x024 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2 <strong>UART</strong>_MDR2<br />
0x028 <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL <strong>UART</strong>_SFLSR <strong>UART</strong>_TXFLL<br />
0x02C <strong>UART</strong>_RESUM <strong>UART</strong>_TXFLH <strong>UART</strong>_RESUME <strong>UART</strong>_TXFLH <strong>UART</strong>_RESUME <strong>UART</strong>_TXFLH<br />
E<br />
0x030 <strong>UART</strong>_SFREG <strong>UART</strong>_RXFLL <strong>UART</strong>_SFREGL <strong>UART</strong>_RXFLL <strong>UART</strong>_SFREGL <strong>UART</strong>_RXFLL<br />
L<br />
0x034 <strong>UART</strong>_SFREG <strong>UART</strong>_RXFLH <strong>UART</strong>_SFREGH <strong>UART</strong>_RXFLH <strong>UART</strong>_SFREGH <strong>UART</strong>_RXFLH<br />
H<br />
(1) REGISTER_NAME(<strong>UART</strong>) notation indicates that the register exists for other functions (IrDA or CIR), but fields have different<br />
meanings for other functions (described separately in , <strong>UART</strong>/IrDA/CIR Register Manual).<br />
(2) REGISTER_NAME[m:n] notation indicates that only register bits numbered m to n apply to the <strong>UART</strong> function.<br />
3650<strong>Universal</strong> <strong>Asynchronous</strong> <strong>Receiver</strong>/<strong>Transmitter</strong> (<strong>UART</strong>) SPRUH73E–October 2011–Revised May 2012<br />
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