Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

Functional Description www.ti.com
TX buffer maximum
Programmable
threshold
Zero byte
DMA active periods;
this does not represent
the DMA signaling.
TX buffer maximum
Programmable
threshold
Zero byte
DMA active periods; this
does not represent the
DMA signaling.
Figure 19-9. Transmit FIFO DMA Request Generation (8 Spaces)
1 character transmitted
1 space
Example: DMA is disabled to
show the end of the transfer.
Characters transmitted from
the UART
8 spaces
The next example shows the setting of one space that uses the DMA for each transfer of one character to
the transmit buffer (see Figure 19-10). The buffer is filled faster than the baud rate at which data is
transmitted to the TX pin. Eventually, the buffer is completely full and the DMA operations stop transferring
data to the transmit buffer.
On two occasions, the buffer holds the maximum amount of data words; shortly after this, the DMA is
disabled to show the slower transmission of the data words to the TX pin. Eventually, the buffer is emptied
at the rate specified by the baud rate settings of the UARTi.UART_DLL and UARTi.UART_DLH registers.
The DMA settings must correspond to the system LH DMA controller settings to ensure correct operation
of this logic.
Figure 19-10. Transmit FIFO DMA Request Generation (1 Space)
Time
Example: DMA is disabled to show the
end of the transfer and the TX buffer emptying.
3644 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
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uart-029
Time
uart-028