Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf
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Functional Description www.ti.com<br />
Figure <strong>19</strong>-31. CIR Pulse Modulation<br />
"01" "011"<br />
T T T T T<br />
12x BAUD<br />
multiple<br />
0.25 or 1/4 duty cycle pulse<br />
0.33 or 1/3 duty cycle pulse<br />
0.42 or 5/12 duty cycle pulse<br />
Nominal T<br />
Effective T length<br />
A minimum of 4 modulation pulses per bit is required by the module.<br />
Based on the requested modulation frequency, the CFPS register must be set with the correct dividing<br />
value to provide the more accurate pulse frequency:<br />
Dividing value = (FCLK/12)/MODfreq<br />
Where FCLK = System clock frequency (48 MHz)<br />
12 = real value of BAUD multiple<br />
MODfreq = Effective frequency of the modulation (MHz)<br />
Example: For a targeted modulation frequency of 36 kHz, the CFPS value must be set to 111 in<br />
decimal which provide an modulation frequency of 36.04 kHz.<br />
Note: The CFPS register is to start with a reset value of 105 (decimal) which translates to a frequency<br />
of 38.1 kHz.<br />
The duty cycle of these pulses is user defined by the pulse duty register bits in the MDR2 configuration<br />
register.<br />
MDR2[5:4] Duty Cycle (High Level)<br />
00 1/4<br />
01 1/3<br />
10 5/12<br />
11 1/2<br />
Figure <strong>19</strong>-32. CIR Modulation Duty Cycle<br />
0.5 or 1/2 duty cycle pulse<br />
3672 <strong>Universal</strong> <strong>Asynchronous</strong> <strong>Receiver</strong>/<strong>Transmitter</strong> (<strong>UART</strong>) SPRUH73E–October 2011–Revised May 2012<br />
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