Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

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Functional Description www.ti.com 19.3.8.1.2 Choosing the Appropriate Divisor Value Two divisor values are: • UART 16x mode: Divisor value = Operating frequency/(16x baud rate) • UART 13x mode: Divisor value = Operating frequency/(13x baud rate) Table 19-25 describes the UART baud rate settings. Table 19-25. UART Baud Rate Settings (48-MHz Clock) Baud Rate Baud Multiple DLH,DLL (Decimal) DLH,DLL (Hex) Actual Baud Rate Error (%) 0.3 kbps 16x 10000 0x27, 0x10 0.3 kbps 0 0.6 kbps 16x 5000 0x13, 0x88 0.6 kbps 0 1.2 kbps 16x 2500 0x09, 0xC4 1.2 kbps 0 2.4 kbps 16x 1250 0x04, 0xE2 2.4 kbps 0 4.8 kbps 16x 625 0x02, 0x71 4.8 kbps 0 9.6 kbps 16x 312 0x01, 0x38 9.6153 kbps +0.16 14.4 kbps 16x 208 0x00, 0xD0 14.423 kbps +0.16 19.2 kbps 16x 156 0x00, 0x9C 19.231 kbps +0.16 28.8 kbps 16x 104 0x00, 0x68 28.846 kbps +0.16 38.4 kbps 16x 78 0x00, 0x4E 38.462 kbps +0.16 57.6 kbps 16x 52 0x00, 0x34 57.692 kbps +0.16 115.2 kbps 16x 26 0x00, 0x1A 115.38 kbps +0.16 230.4 kbps 16x 13 0x00, 0x0D 230.77 kbps +0.16 460.8 kbps 13x 8 0x00, 0x08 461.54 kbps +0.16 921.6 kbps 13x 4 0x00, 0x04 923.08 kbps +0.16 1.843 Mbps 13x 2 0x00, 0x02 1.846 Mbps +0.16 3.6884 Mbps 13x 1 0x00, 0x01 3.6923 Mbps +0.16 19.3.8.1.3 UART Data Formatting The UART can use hardware flow control to manage transmission and reception. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. The UART is enhanced with the autobauding function. In control mode, autobauding lets the speed, the number of bits per character, and the parity selected be set automatically. 19.3.8.1.3.1 Frame Formatting When autobauding is not used, frame format attributes must be defined in the UARTi.UART_LCR register. Character length is specified using the UARTi.UART_LCR[1:0] CHAR_LENGTH bit field. The number of stop-bits is specified using the UARTi.UART_LCR[2] NB_STOP bit. The parity bit is programmed using the UARTi.UART_LCR[5:3] PARITY_EN, PARITY_TYPE_1, and PARITY_TYPE_2 bit fields (see Table 19-26). Table 19-26. UART Parity Bit Encoding PARITY_EN PARITY_TYPE_1 PARITY_TYPE_2 Parity 0 N/A N/A No parity 1 0 0 Odd parity 1 1 0 Even parity 1 0 1 Forced 1 1 1 1 Forced 0 3654 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
www.ti.com Functional Description 19.3.8.1.3.2 Hardware Flow Control Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled and disabled independently by programming the UARTi.UART_EFR[7:6] AUTO_CTS_EN and AUTO_RTS_EN bit fields, respectively. With auto-CTS, uarti_cts must be active before the module can transmit data. Auto-RTS activates the uarti_rts output only when there is enough room in the RX FIFO to receive data. It deactivates the uarti_rts output when the RX FIFO is sufficiently full. The HALT and RESTORE trigger levels in the UARTi.UART_TCR register determine the levels at which uarti_rts is activated and deactivated. If auto-CTS and auto-RTS are enabled, data transmission does not occur unless the RX FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If auto-CTS and auto-RTS are not enabled, overrun errors occur if the transmit data rate exceeds the RX FIFO latency. • Auto-RTS: Auto-RTS data flow control originates in the receiver block. The RX FIFO trigger levels used in auto- RTS are stored in the UARTi.UART_TCR register. uarti_rts is active if the RX FIFO level is below the HALT trigger level in the UARTi.UART_TCR[3:0] RX_FIFO_TRIG_HALT bit field. When the RX FIFO HALT trigger level is reached, uarti_rts is deasserted. The sending device (for example, another UART) can send an additional byte after the trigger level is reached because it may not recognize the deassertion of RTS until it begins sending the additional byte. uarti_rts is automatically reasserted when the RX FIFO reaches the RESUME trigger level programmed by the UARTi.UART_TCR[7:4] RX_FIFO_TRIG_START bit field. This reassertion requests the sending device to resume transmission. In this case, uarti_rts is an active-low signal. • Auto-CTS: The transmitter circuitry checks uarti_cts before sending the next data byte. When uarti_cts is active, the transmitter sends the next byte. To stop the transmitter from sending the next byte, uarti_cts must be deasserted before the middle of the last stop-bit currently sent. The auto-CTS function reduces interrupts to the host system. When auto-CTS flow control is enabled, the uarti_cts state changes do not have to trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO, and a receiver overrun error can result. In this case, uarti_cts is an active-low signal. 19.3.8.1.3.3 Software Flow Control Software flow control is enabled through the enhanced feature register (UARTi.UART_EFR) and the modem control register (UARTi.UART_MCR). Different combinations of software flow control can be enabled by setting different combinations of the UARTi.UART_EFR[3:0] bit field (see Table 19-27). Two other enhanced features relate to software flow control: • XON any function (UARTi.UART_MCR[5]): Operation resumes after receiving any character after the XOFF character is recognized. If special character detect is enabled and special character is received after XOFF1, it does not resume transmission. The special character is stored in the RX FIFO. NOTE: The XON-any character is written into the RX FIFO even if it is a software flow character. • Special character (UARTi.UART_EFR[5]): Incoming data is compared to XOFF2. When the special character is detected, the XOFF interrupt (UARTi.UART_IIR[4]) is set, but it does not halt transmission. The XOFF interrupt is cleared by a read of UARTi.UART_IIR. The special character is transferred to the RX FIFO. Special character does not work with XON2, XOFF2, or sequential XOFFs. SPRUH73E–October 2011–Revised May 2012 Universal Asynchronous Receiver/Transmitter (UART) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 3655
Page 1 and 2: Chapter 19 SPRUH73E-October 2011-Re
Page 3 and 4: www.ti.com Introduction Table 19-1.
Page 5 and 6: www.ti.com Integration Table 19-2.
Page 7 and 8: www.ti.com Integration 19.2.3 UART
Page 9 and 10: www.ti.com Functional Description L
Page 11 and 12: www.ti.com Functional Description T
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Page 23 and 24: www.ti.com Functional Description C
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Page 41 and 42: www.ti.com Functional Description
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Page 51 and 52: www.ti.com UART/IrDA/CIR Basic Prog
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www.ti.com UART Registers 19.5.1.23
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www.ti.com UART Registers EFR[3:0]
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