Chapter 19 Universal Asynchronous Receiver-Transmitter (UART).pdf

Functional Description www.ti.com
19.3.8.3.4 Frequency Divider Values
The data transferred is a succession of pulse with a T period. Depending on the standards used, the T
period is defined through the DLL and DLH registers which defined the value to divide the functional clock
(48 MHz):
Dividing value = (FCLK/16)/Tfreq
Where FCLK = System clock frequency (48 MHz)
16 = real value of BAUD multiple
Tfreq = Effective frequency of the T pulse (MHz)
In an example case using a variable pulse duration definitions:
Data in FIFO
Figure 19-33. Variable Pulse Duration Definitions
T
1 0
For a logical “1”, the pulse duration is equal to 2T and for a logical “0”, it’s equal to 4T.
If T =0.56 ms, the value coded into the DLH and DLL register must be 1680 in decimal.
3674 Universal Asynchronous Receiver/Transmitter (UART) SPRUH73E–October 2011–Revised May 2012
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
1
1
0
0