A Wavelength Converter Integrated with a Discretely Tunable Laser ...
A Wavelength Converter Integrated with a Discretely Tunable Laser ...
A Wavelength Converter Integrated with a Discretely Tunable Laser ...
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74 5. Technology<br />
only a thin layer of resist (typically 300 nm) remains on the top of the SOA. During<br />
the lithography, all negative resist outside the active regions is exposed. Therefore, only<br />
the resist in the active regions dissolves during development. However, the whole resist<br />
column in the active regions is dissolvable and the development process must last just<br />
long enough to open the top of the ridge. The key parameters that must be controlled<br />
in this process are the uniformity of the thickness of the resist over the wafer and the<br />
uniformity and reproducibility of the development speed over the wafer. An advantage<br />
of this process is that if the resist is not developed deep enough, it can be developed<br />
further.<br />
d) Plasma. A third self aligned method uses an O ¦ plasma in stead of developer to remove<br />
resist from the SOA waveguide tops. This method does not use a mask nor UV-exposure.<br />
A relatively thin layer of resist is spun such that only about 100 nm of resist or even no<br />
resist on top of the SOA mesa is left. Next, the resist is etched from the SOA tops in<br />
an O ¦ plasma, followed by a buffered HF etch that removes the SiN from the tops. In<br />
this method there is no distinction between active and passive regions apart from their<br />
geometry, i.e. the passive waveguides are about 600 nm lower than the SOAs. The main<br />
problem is that the resist should not be removed from the passive waveguides, but this is<br />
very hard to verify using a microscope.<br />
This process does not work on wide ( waveguides 4 ), because during spinning the<br />
resist sees them as planar surfaces, and the resist on top the ridges will be as thick as<br />
next to the ridges. Only the SiN on top of the ridges is removed and it remains on the<br />
rest of the wafer. This may cause the wafer to bow the SiN is strained.<br />
If contact openings are defined on narrow SOAs using a self-aligned contact opening process,<br />
then it must be taken into account that the metalization step that follows must be compatible<br />
<strong>with</strong> narrow ridges. This excludes a planarization step <strong>with</strong> low resolution polyimide on ridges<br />
of £¥ , and only a metalization that results in step coverage can be used (sputtering or<br />
evaporation on a tilted an rotating wafer).<br />
In summary, for the fabrication of contact openings in SiN on SOA ridges 2.0 , the<br />
standard method ”a” works fine. Methods ”c” and ”d” were found to be intolerant and hard<br />
to reproduce. For SOA ridges 2.0 method ”b” is suggested as the most tolerant and<br />
reproducible method.