Download complete software manual (PDF-File) - esd electronics, Inc.
Download complete software manual (PDF-File) - esd electronics, Inc.
Download complete software manual (PDF-File) - esd electronics, Inc.
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ip<br />
tp<br />
ar wr<br />
op<br />
Further parameters not shown:<br />
opol = 0<br />
tedg = 2<br />
gp = 0<br />
Fig. 4.3.12: Timing example for OSC operation<br />
Pulse Processing Mode<br />
Following the active edge of trigger input tp the register wr is counted up (with mode = 10) or<br />
down (with mode = 111) via the input cycle (ip).<br />
If the value of the register wr reaches the value of the register ar, register wr is reset and the output<br />
signal (op) is inverted. This status is retained until the next trigger pulse is received. After the<br />
reception of the trigger the output is again inverted and the counting process is started again.<br />
VME DPIO32 Software Manual Rev. 2.1 49