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58
Pulse Processing Mode
4.3.19 SPO - shift parallel output
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* mode 5crd * op *opol* ip *iedg* tp *tedg* gp *mode*fnr * wr * ar *prld*
G444444>4444P4444P4444P4444P4444P4444P4444P4444P4444P4444P4444P4444P4444I
* SPO 51-16* 1*)*0/1 * 2*)*0-3 * 3*)*0-3 * 0 * 16 *1-32*1-48*1-64*STC**
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Parameters fnr, wr, ar, and prld will be explained in detail following the description of the parameter mode.
4.3.201*) In this function the output pins on which the bits of the shift register (wr) are to be put out are selected via
the parameter op. The coding of the op becomes clear when the parameter is regarded as five-digit
binary number. The transition still occurs as FIXED variable. The following table shows the bit-to-pinassignment.
The bits O0 to O4 are assigned to the bits of the parameter op as follows:
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
O4 O3 O2 O1 O0
O0 = 1
O1 = 1
O2 = 1
O3 = 1
O4 = 1 O4 = 0
shift-register
output pin
shift-register
output pin
bit
HD1 (HD2)
bit
HD1 (HD2)
Table 4.3.7: Output pins in SPO mode
0 < 1 (17) 0 < 33 (41)
1 < 2 (18) 1 < 34 (42)
2 < 3 (19) 2 < 35 (43)
3 < 4 (20) 3 < 36 (44)
4 < 5 (21) 4 < 37 (45)
5 < 6 (22) 5 < 38 (46)
6 < 7 (23) 6 < 39 (47)
7 < 8 (24) 7 < 40 (48)
Via O4=1 real pins are selected as output and via O4=0 hidden pins are selected. The real pins 9 to 16 (or 25 to
32) cannot be selected!
If the bits O0...O3 are set to '0', the bits of the shift register are not output.
Example: Via op = 17 the shift-register bits 0 to 5 are output on the output pins 1 to 6.
It has to be taken care of that the pin direction of the real pins, as selected in the software, corresponds to the
connected signals!
2*) 'Real pins', 'hidden pins' or the internal cycle can be used as input pins:
VME DPIO32 Software Manual Rev. 2.1