Synergy User Manual and Tutorial. - THE CORE MEMORY

Synergy User Manual and Tutorial
of the chip had symmetric dual processing—the ability to have two processors in the
same system.
In 1995, the Pentium Pro was released with 5.5 million
transistors, a 0.6-micron die and a clock speed of up to 200
MHz. It was a reduced instruction set computer (RISC)
processor. RISC processors have a smaller set of instructions
than complex instruction set computer processors. The first
computers were of CISC design to bridge semantic differences
or gaps between low-level machine code and high-level
programming languages, which reduced the size of computer
programs and calls to main memory but did not necessarily
improve system performance. The main idea with RISC is to build more complex
instructions using a sequence of smaller, simpler instructions. Complex instructions have
greater time and space overhead while decoding instructions, especially when microcode
is used to decode macroinstructions. There is a high probability that the frequency of
instructions to be processed will be smaller rather than larger. Limiting the number of
instructions in a computer to a smaller optimized set can contribute to greater
performance. The Pentium Pro could process three instructions per clock cycle and had
decoupled decoding and execution, which allowed the processor to keep working on
instructions in other pipelines if one of the pipelines stops to wait for an event. The
standard Pentium would stop all pipelines until the event occurred. It also had up to 1
MB of onboard level-2 cache, which was faster than having the cache on the
motherboard.
In 1997, Intel released the Pentium MMX series of processors
with 4.5 million transistors, clock speeds up to 233 MHz and a
0.35-micron die size. The MMX had 57 additional complex
instructions that aided the CPU in performing multimedia and
gaming instructions 10 to 20 percent faster than processors
without the MMX instruction set. The processor also had dual
16K level-1 cache and improved dynamic branch prediction, an
additional instruction pipe and a pipelined FPU.
In 1993, Intel released the Pentium II, which had 27.4
million transistors and a 0.25-micron die. The
Pentium II combined technology from both the
Pentium Pro and the Pentium MMX. It had the Pro’s
dynamic branch prediction, the MMX instructions,
dual 16K level-1 cache and 512K of level-2 cache.
The level-2 cache ran at ½-speed and was not
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