Synergy User Manual and Tutorial. - THE CORE MEMORY

Synergy User Manual and Tutorial
all memories (possibly stores each cell of an array or each column of a matrix in a
different memory area). These machines are designed to execute arithmetic and data
operations on a large number of data elements very quickly. A vector machine can
perform operations in constant time if the length of the vectors (arrays) does not exceed
the number of data processors. Most supercomputers, used for scientific computing in
the 1980’s and 1990’s, are based on this architecture.
Multiple instruction streams/single data stream (MISD) systems have multiple instruction
processors and a single data processor. Few of these machines have been produced and
have had no commercial success.
Multiple instruction streams/multiple data streams (MIMD) systems have multiple
instruction processors and multiple data processors. There are a diverse variety of MIMD
systems including those constructed from inexpensive off-the-shelf components to much
more expensive interconnected vector processors, and many other configurations.
Computers over a network that simultaneously cooperate to complete a single task are
MIMD systems. Computers that have two or more independent processors are another
example. A multiple independent processor machine has the ability to perform more than
one task, simultaneously. lvii
There are three types of performance gains received from parallel processing solutions
for the use of n processors:
• Sub-linear speedup is when the increase in speed is less than
o i.e. five processors yields only 3x speedup
• Linear speedup is when the increase is equal to n
o i.e. five processors yields 5x speedup
• Super-linear speedup is when the increase is greater than n
o i.e. five processors yields 7x speedup
Generally linear or faster speedup is very hard to achieve because of the sequential nature
of most algorithms. Parallel algorithms must be designed to take advantage of parallel
hardware. Parallel systems may have one shared memory area, to which all processors
may have access. In shared memory systems care must be taken to design parallel
algorithms that ensure mutual exclusion, which protects data from being corrupted when
operated on by more than one processor. The results from parallel operations should be
determinate, meaning they should be the same as if done by a sequential algorithm. As
an example, if two processors write to the same variable in memory such that:
• Processor 1 reads: x
• Processor 2 reads: x
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