ARM710T processor

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Mnemonic Instruction Action STM Store Multiple Stack manipulation (Push) STR Store register to memory := Rd SUB Subtract Rd := Rn - Op2 SWI Software Interrupt OS call SWP Swap register with memory Rd := [Rn], [Rn] := Rm TEQ Test bitwise equality CPSR flags := Rn EOR Op2 TST Test bits CPSR flags := Rn AND Op2 Table 1-1: ARM instruction summary (Continued) 1-7
1.4.2 THUMB Instruction Set This section gives an overview of the THUMB instructions available. For full details of these instructions, please refer to the ARM Architecture Reference Manual (ARM DDI 0100). Format summary The THUMB instruction set formats are shown in Figure 1-3: THUMB instruction set formats. Move shifted register Add/subtract Move/compare/add/subtract immediate ALU operations Hi register operations/branch exchange PC-relative load Load/store with register offset Load/store sign-extended byte/halfword Load/store with immediate offset Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop registers Multiple load/store Conditional branch Software Interrupt Unconditional branch Long branch with link 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 1 0 0 0 Op Offset5 Rs Rd 2 0 0 0 1 1 I Op Rn/offset3 Rs Rd 3 0 0 1 Op Rd Offset8 4 0 1 0 0 0 0 Op Rs Rd 5 0 1 0 0 0 1 Op H1 H2 Rs/Hs Rd/Hd 6 0 1 0 0 1 Rd Word8 7 0 1 0 1 L B 0 Ro Rb Rd 8 0 1 0 1 H S 1 Ro Rb Rd 9 0 1 1 B L Offset5 Rb Rd 10 1 0 0 0 L Offset5 Rb Rd 11 1 0 0 1 L Rd Word8 12 1 0 1 0 SP Rd Word8 13 1 0 1 1 0 0 0 0 S SWord7 14 1 0 1 1 L 1 0 R Rlist 15 1 1 0 0 L Rb Rlist 16 1 1 0 1 Cond Soffset8 17 1 1 0 1 1 1 1 1 Value8 18 1 1 1 0 0 Offset11 19 1 1 1 1 H Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 1-3: THUMB instruction set formats 1-8
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9: ARM instruction summary Table 1-1:
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

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