ARM710T processor

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1.2 Block Diagram Virtual Address Bus 8 KB MMU Cache ARM7TDMI CPU JTAG Debug Interface Internal Data Bus Coprocessor Interface Data and Address Buffers AMBA Interface Control and Clocking Logic System Control Coprocessor AMBA Bus Interface 1.3 Coprocessors Figure 1-1: ARM710T block diagram The ARM710T still has an internal coprocessor designated #15 for internal control of the device. See 4.3 Registers on page 4-4 for a complete description. ARM710T also includes a port for the connection of on-chip coprocessors. This allows the functionality of the ARM710T to be extended in an architecturally consistent manner. 1-3
1.4 Instruction Set Overview The instruction set comprises ten basic instruction types: • Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform high-speed operations on the data in a bank of 31 registers, each 32 bits wide. • Three classes of instruction control data transfer between memory and the registers, one optimised for flexibility of addressing, another for rapid context switching and the third for swapping data. • Two instructions control the flow and privilege level of execution. • Three types are dedicated to the control of external coprocessors which allow the functionality of the instruction set to be extended off-chip in an open and uniform way. The ARM instruction set is a good target for compilers of many different high-level languages. Where required for critical code segments, assembly code programming is also straightforward, unlike some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. 1-4
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5: 1.1 Overview The ARM710T is a gener
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

ARM710T processor

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