ARM710T processor

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4.3.6 Register 5: Fault Status Register Note Reading CP15, register 5 returns the value of the Fault Status Register (FSR). The FSR contains the source of the last data fault. Only the bottom 9 bits are returned. The upper 23 bits are UNPREDICTABLE. The FSR indicates the domain and type of access being attempted when an abort occurred: Bit 8 is always read as zero. Bit 8 is ignored on writes. Bits [7:4] specify which of the 16 domains (D15–D0) was being accessed when a fault occurred. Bits [3:1] indicate the type of access being attempted. The encoding of these bits is shown in 8.12 Fault Address & Fault Status Registers (FAR & FSR) on page 8-14. The FSR is only updated for data faults, not for prefetch faults. Writing CP15, register 5 sets the Fault Status Register to the value of the data written. This is useful when a debugger needs to restore the value of the FSR. The upper 24 bits written SHOULD BE ZERO. The CRm and opcode_2 fields SHOULD BE ZERO when reading or writing CP15 register 5. 31 UNP/SBZ 9 8 7 4 3 0 Domain Status 0 Figure 4-9: Register 5 4.3.7 Register 6: Fault Address Register Reading CP15, register 6 returns the value of the Fault Address Register (FAR). The FAR holds the virtual address of the access which was attempted when a fault occurred. The FAR is only updated for data faults, not for prefetch faults. Writing CP15, register 6 sets the Fault Address Register to the value of the data written. This is useful when a debugger needs to restore the value of the FAR. The CRm and opcode_2 fields SHOULD BE ZERO when reading or writing CP15 register 6. 31 0 Fault Address Figure 4-10: Register 6 4-7
4.3.8 Register 7: Cache Operations Writing to CP15, register 7 is used to manage the <strong>ARM710T</strong>’s unified instruction and data cache. Only one cache operation is defined using the following opcode_2 and CRm fields in the MCR instruction used to write CP15 register 7: 4.3.9 Register 8: TLB Operations Function opcode_2 value CRm value Data Instruction Invalidate ID cache 0b000 0b0111 SBZ MCR p15, 0, Rd, c7, c7, 0 Reading from CP15 register 7 is UNDEFINED. Table 4-2: Cache operation The “Invalidate ID cache” function invalidates all cache data. Use with caution. Writing to CP15, register 8 is used to control the Translation Lookaside Buffer (TLB). The <strong>ARM710T</strong> implements a unified instruction and data TLB. Two TLB operations are defined, and the function to be performed selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8. Function opcode_2 value CRm value Data Instruction Invalidate TLB 0b000 0b0111 SBZ MCR p15, 0, Rd, c8, c7, 0 Invalidate TLB single entry 0b001 0b0111 Virtual Address MCR p15, 0, Rd, c8, c7, 1 4.3.10 Registers 9 - 15: Reserved Reading from CP15, register 8 is UNDEFINED. Table 4-3: TLB operations The “Invalidate TLB” function invalidates all of the unlocked entries in the TLB The “Invalidate TLB single entry” function invalidates any TLB entry corresponding to the Virtual Address given in Rd. Accessing any of these registers is undefined. Writing to any of these registers is undefined. 4-8
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43: Enabling the MMU Care must be taken
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

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