ARM710T processor

Name Type Source/
Destination
Description
BSIZE[1:0] Out Current bus master Bus Size
These signals indicate the size of the transfer, which may be byte,
halfword or word. These signals have the same timing as the address
bus.
BTRAN[1:0] Out Bus master Bus Transaction Type
These signals indicate the type of the next transaction which may be
address-only, nonsequential or sequential. These signals are driven
when AGNT is asserted, and are valid during the high phase of BCLK
before the transfer to which they refer.
BWAIT InOut System decoder
and
current bus master
Bus Wait
This signal is driven by the selected slave to indicate if the current
transfer may complete. If BWAIT is HIGH, a further bus cycle is
required. If BWAIT is LOW, the current transfer may complete in the
current bus cycle.
BWRITE InOut Current bus master Bus Write
When HIGH, this signal indicates a bus write cycle and when LOW, a
read cycle. This signal has the same timing as the address bus.
DSEL In System decoder Slave Select
This signal puts the ARM core into a test mode so that vectors can be
written in and out of the core.
Table 2-1: ASB signal descriptions (Continued)
2-3