ARM710T processor

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4.3.2 Register 1: Control register Reading from CP15 register 1 reads the control bits. The CRm and opcode_2 fields SHOULD BE ZERO when reading CP15 register 1. 9 8 7 6 5 4 3 2 1 0 UNP R S B L D P W C A M Figure 4-4: Register 1 read Writing to CP15 register 1 sets the control bits. The CRm and opcode_2 fields SHOULD BE ZERO when writing CP15 register 1. 9 8 7 6 5 4 3 2 1 0 UNP/SBZ R S B L D P W C A M Figure 4-5: Register 1 write All defined control bits are set to zero on reset. The control bits have the following functions: M Bit 0 MMU Enable/Disable 0 = Memory Management Unit (MMU) disabled 1 = Memory Management Unit (MMU) enabled A Bit 1 Alignment Fault Enable/Disable 0= Address Alignment Fault Checking disabled 1 = Address Alignment Fault Checking enabled C Bit 2 Cache Enable/Disable 0 = Instruction and/or Data Cache (IDC) disabled 1 = Instruction and/or Data Cache (IDC) enabled W Bit 3 Write buffer Enable/Disable 0 = Write Buffer disabled 1 = Write Buffer enabled P Bit 4 When read, returns one; when written, is ignored. D Bit 5 When read, returns one; when written, is ignored. L Bit 6 When read, returns one; when written, is ignored. B Bit 7 Big-endian/little-endian 0 = Little-endian operation 1 = Big-endian operation S Bit 8 System protection Modifies the MMU protection system. R Bit 9 ROM protection Modifies the MMU protection system. Bits 31:10 When read, this returns an UNPREDICTABLE value, and when written, it SHOULD BE ZERO, or a value read from these bits on the same <strong>processor</strong>. Note that using a read-write-modify sequence when modifying this register provides the greatest future compatibility. 4-5
Enabling the MMU Care must be taken if the translated address differs from the untranslated address, because the instructions following the enabling of the MMU will have been fetched using no address translation; enabling the MMU may be considered as a branch with delayed execution. A similar situation occurs when the MMU is disabled. The correct code sequence for enabling and disabling the MMU is given in 8.16 Interaction of the MMU, IDC and Write Buffer on page 8-20. If the cache and write buffer are enabled when the MMU is not enabled, the results are UNPREDICTABLE. 4.3.3 Register 2: Translation table base register Reading from CP15 register 2 returns the pointer to the currently active first-level translation table in bits [31:14] and an UNPREDICTABLE value in bits [13:0].The CRm and opcode_2 fields SHOULD BE ZERO when reading CP15 register 2. Writing to CP15 register 2 updates the pointer to the currently active first-level translation table from the value in bits [31:14] of the written value. Bits [13:0] SHOULD BE ZERO. The CRm and opcode_2 fields SHOULD BE ZERO when writing CP15 register 2. 31 14 13 0 Translation Table Base UNP/SBZ 4.3.4 Register 3: Domain access control register Figure 4-6: Register 2 Reading from CP15, register 3 returns the value of the Domain Access Control Register. Writing to CP15, register 3 writes the value of Domain Access Control Register. The Domain Access Control Register consists of 16 2-bit fields, each of which defines the access permissions for one of the 16 Domains (D15–D0). The CRm and opcode_2 fields SHOULD BE ZERO when reading or writing CP15 register 3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 4.3.5 Register 4: Reserved Figure 4-7: Register 3 Register 4 is reserved. Reading CP15, register 4 is UNDEFINED. Writing CP15, register 4 is UNDEFINED. 31 0 UNP Figure 4-8: Register 4 4-6
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41: 4.3 Registers ARM710T contains regi
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

ARM710T processor

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