ARM710T processor

5.2 IDC Validity
5.2.1 Software IDC flush
5.2.2 Doubly-mapped space
The IDC operates with virtual addresses, so you must ensure that its contents remain
consistent with the virtual to physical mappings performed by the Memory
Management Unit. If the memory mappings are changed, the IDC validity must be
ensured.
The entire IDC may be marked as invalid by using the ARM710T Cache Operations
Register (register 7). The cache is flushed immediately the register is written, but note
that the two instruction fetches following may come from the cache before the register
is written.
As the cache works with virtual addresses, it is assumed that every virtual address
maps to a different physical address. If the same physical location is accessed by more
than one virtual address, the cache cannot maintain consistency, because each virtual
address has a separate entry in the cache, and only one entry can be updated on a
processor write operation.
To avoid any cache inconsistencies, both doubly-mapped virtual addresses should be
marked as uncacheable.
5-3