ARM710T processor

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Name Type Description nCPI Out Not Coprocessor Instruction When LOW, this signal indicates that the ARM710T is executing a coprocessor instruction. nOPC In Not OPcode Fetch When LOW, this signal indicates that the processor is fetching an instruction from memory. When HIGH, data (if present) is being transferred. This signal is used by the coprocessor to track the ARM pipeline. nUSER Out Not User Mode When LOW, this signal indicates that the processor is in user mode. It is used by a coprocessor to qualify instructions. TBIT Out Thumb Mode This signal, when HIGH, indicates that the processor is executing the THUMB instruction set. When LOW, the processor is executing the ARM instruction set. Table 2-2: Coprocessor interface signal descriptions (Continued) 2-5
2.3 JTAG Signals Name Type Description HIGHZ Out High Z This signal denotes that the HIGHZ instruction has been loaded into TAP controller. IR[3:0] Out TAP Instruction Register These signals reflect the current instruction loaded into the TAP controller instruction register. The signals change on the falling edge of XTCK when the TAP state machine is in the UPDATEDR state. These signals may be used to allow more scan chains to be added using the ARM710T TAP controller. RSTCLKBS Out Reset Boundary Scan Clock This signal denotes that either the TAP controller state machine is in the RESET state or that XNtrst has been asserted. This may be used to reset boundary scan cells outside the ARM710T SCREG[3:0] Out Scan Chain Register These signals reflect the ID number of the scan chain currently selected by the TAP controller. These signals change on the falling edge of XTCK when the TAP state machine is in the UPDATE-DR state. SDINBS Out Boundary Scan Serial Data In This signal is the serial data to be applied to an external scan chain. SDOUTBS In Boundary Scan Serial Data Out This signal is the serial data from an external scan chain. It allows a single XTDO port to be used. If an external scan chain is not connected, this input should be tied LOW. TAPSM[3:0] Out Tap Controller Status These signals represent the current state of the TAP controller machine. These signals change on the rising edge of XTCK and may be used to allow more scan chains to be added using the ARM710T TAP controller. TCK1 Out Test Clock 1 This clock represents the HIGH phase of XTCK. TCK1 is HIGH when XTCK is HIGH. This signal may be used to allow more scan chains to be added using the ARM710T TAP controller. TCK2 Out Test Clock 2 This clock represents the LOW phase of XTCK. TCK2 is HIGH when XTCK is LOW. This signal may be used to allow more scan chains to be added using the ARM710T TAP controller. TCK2 is the non-overlapping complement of TCK1. Table 2-3: JTAG signal descriptions 2-6
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17: 2.2 Coprocessor Interface Signals N
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

ARM710T processor

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