ARM710T processor

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6 Write Buffer This chapter describes the Write Buffer. 6.1 Overview 6-2 6.2 Write Buffer Operation 6-3 6-1
6.1 Overview Note 6.1.1 Bufferable bit The <strong>ARM710T</strong> write buffer is provided to improve system performance. It can buffer up to eight words of data, and four independent addresses. It may be enabled or disabled via the W bit (bit 3) in the <strong>ARM710T</strong> Control Register. The buffer is disabled and flushed on reset. The operation of the write buffer is further controlled by the Bufferable (B) bit, which is stored in the Memory Management Page Tables. For this reason, the MMU must be enabled so you can use the write buffer. The two functions may however be enabled simultaneously, with a single write to the Control Register. For a write to use the write buffer, both the W bit in the Control Register and the B bit in the corresponding page table must be set. It is not possible to abort buffered writes externally; the BERROR pin is ignored. Areas of memory which may generate aborts should be marked as unbufferable in the MMU page tables. This bit controls whether a write operation may or may not use the write buffer. Typically main memory will be bufferable and I/O space unbufferable. The Bufferable bit can be configured for both pages and sections. 6-2
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49: 5.3 IDC Enable/Disable and Reset Th

ARM710T processor

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