ARM710T processor

2.5 Miscellaneous Signals
Name Type Source/
Destination
Description
BIGEND Out Configuration Input Big-endian Format
When this signal is HIGH, the processor treats bytes in memory as
being in big-endian format. When it is LOW, memory is treated as
little-endian.
FCLK In External Clock
source
Fast Clock input
This clock is used to clock the ARM core when XFASTBUS is LOW.
During testing, the signal allows efficient testing of the RAM, TAG and
MMU blocks.
XFASTBUS In Configuration Input Bus clocking Mode Configuration Signal
When HIGH the ARM710T operates from a single clock, BCLK.
When LOW selects standard mode operating from two clocks, BCLK
and FCLK.
XNFIRQ In Interrupt controller ARM Fast Interrupt Request Signal
XnIRQ In Interrupt controller ARM Interrupt Request Signal
The interrupt controller mixes several interrupt sources, and produces
XNIRQ
XSnA In Configuration Input Synchronous/not Asynchronous Configuration Pin
In standard ARM bus mode this signal determines the bus interface
mode and should be wired HIGH or LOW depending on the desired
relationship between FCLK and BCLK. See 10.3 Standard Mode.
This pin is ignored when operating with the fastbus extension.
Table 2-5: Miscellaneous signal descriptions
2-9