ARM710T processor

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5 Instruction and Data Cache (IDC) This chapter describes the instruction and data cache. 5.1 Overview of the Instruction and Data Cache 5-2 5.2 IDC Validity 5-3 5.3 IDC Enable/Disable and Reset 5-4 5-1
5.1 Overview of the Instruction and Data Cache ARM710T contains an 8KB mixed instruction and data cache (IDC). The IDC has 512 lines of 16 bytes (four words), arranged as a four-way set-associative cache, and uses the virtual addresses generated by the processor core. The IDC is always reloaded a line at a time (four words). It may be enabled or disabled via the ARM710T Control Register and is disabled on BnRES. The operation of the cache is further controlled by the Cacheable (C) bit stored in the Memory Management Page Table (see Chapter 8, Memory Management Unit (MMU)). For this reason, the MMU must be enabled in order to use the IDC. The two functions may, however, be enabled simultaneously, with a single write to the Control Register. 5.1.1 IDC operation 5.1.2 Cacheable bit The C bit in the ARM710T Control Register and the Cacheable bit in the MMU page tables only affect loading data into the Cache. The Cache is always searched regardless of these two bits, and if the data is found, it is used, so when the cache is disabled, it should also be flushed. The Cacheable bit determines whether data being read may be placed in the IDC and used for subsequent read operations. Typically, main memory is marked as cacheable to improve system performance, and I/O space as non-cacheable to stop the data being stored in ARM710T’s cache. For example, if the processor is polling a hardware flag in I/O space, it is important that the processor is forced to read data from the external peripheral, and not a copy of the initial data held in the cache. The Cacheable bit can be configured for both pages and sections. 5.1.3 Read-lock-write Cacheable reads (C = 1) A linefetch of four words is performed when a cache miss occurs in a cacheable area of memory, and it will be randomly placed in a cache bank. Uncacheable reads (C = 0) An external memory access is performed and the cache will not be written. The IDC treats the Read-Locked-Write instruction as a special case. The read phase always forces a read of external memory, regardless of whether the data is contained in the cache. The write phase is treated as a normal write operation (and if the data is already in the cache, the cache will be updated). Externally the two phases are flagged as indivisible by asserting the BLOK signal. 5-2
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13 and 14: Mnemonic Instruction Lo register op
Page 15 and 16: 2.1 AMBA Interface Signals Name Typ
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45: 4.3.8 Register 7: Cache Operations
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

ARM710T processor

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