ARM710T processor

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2 Signal Descriptions This chapter describes the interface signals of ARM710T. 2.1 AMBA Interface Signals 2-2 2.2 Coprocessor Interface Signals 2-4 2.3 JTAG Signals 2-6 2.4 Debugger Signals 2-8 2.5 Miscellaneous Signals 2-9 2-1
2.1 AMBA Interface Signals Name Type Source/ Destination Description AGNT In Arbiter Access Grant. This signal from the bus arbiter indicates that the bus master is currently the highest priority master requesting the bus. If AGNT is asserted at the end of a transfer (BWAIT LOW), the master is granted the bus AGNT changes during the low phase of BCLK, and remains valid through the high phase. AREQ Out Arbiter Access Request This signal indicates that the master requires the bus. It changes during the high phase of BCLK. This signal is intended for use where the ARM710T is not the lowest priority or default bus master. BA[31:0] Out Current bus master Bus Address. This is the system address bus BCLK In System (bus) Clock This clock times all bus transfers. BD[31:0] InOut Bus master Bidirectional system data bus This is the data bus is driven by the current bus master during write cycles, and by the appropriate bus slave during read cycles. BERROR InOut System decoder and current bus master BLAST InOut System decoder and current bus master Bus Error This signal indicates a transfer error by the selected bus slave using the BERROR signal. When BERROR is HIGH, a transfer error has occurred. When BERROR is LOW, the transfer is successful. This signal is also used in combination with the BLAST signal to indicate a bus retract operation. Bus Class This signal is driven by the selected slave to indicate if the current transfer should be the last of a burst sequence. When BLAST is HIGH the next bus transfer must allow for sufficient time for address decoding. When BLAST is LOW, the next transfer may continue as a burst sequence. This signal is also used in combination with the BERROR signal to indicate a bus retract operation. BLOK Out Arbiter Bus Clock When HIGH, this signal indicates that the following bus transfer is to be indivisible and no other bus master should be given access to the bus. BnRES In Reset state machine Bus Reset This signal indicates the reset status of the bus. BPROT[1:0] Out System decoder Bus Protections These signals provide additional information about the transfer being performed. All write cycles are indicated as being Supervisor accesses. These signals have the same timing as the BA signals. Table 2-1: ASB signal descriptions 2-2
Page 1 and 2: ARM710T processor ARM7TDMI CPU with
Page 3 and 4: 5.2 IDC Validity 5-3 5.3 IDC Enable
Page 5 and 6: 1.1 Overview The ARM710T is a gener
Page 7 and 8: 1.4 Instruction Set Overview The in
Page 9 and 10: ARM instruction summary Table 1-1:
Page 11 and 12: 1.4.2 THUMB Instruction Set This se
Page 13: Mnemonic Instruction Lo register op
Page 17 and 18: 2.2 Coprocessor Interface Signals N
Page 19 and 20: 2.3 JTAG Signals Name Type Descript
Page 21 and 22: 2.4 Debugger Signals Name Type Desc
Page 23 and 24: 3 Programmer’s Model This chapter
Page 25 and 26: 3.2 Memory Formats 3.2.1 Big-endian
Page 27 and 28: 3.4 Registers ARM710T has a total o
Page 29 and 30: 3.4.2 The THUMB state register set
Page 31 and 32: 3.5 The Program Status Registers Th
Page 33 and 34: 3.6 Exceptions 3.6.1 Action on ente
Page 35 and 36: 3.6.5 IRQ 3.6.6 Abort Note The Inte
Page 37 and 38: 3.7 Reset When the BnRES signal goe
Page 39 and 40: 4.1 Overview The operation and conf
Page 41 and 42: 4.3 Registers ARM710T contains regi
Page 43 and 44: Enabling the MMU Care must be taken
Page 45 and 46: 4.3.8 Register 7: Cache Operations
Page 47 and 48: 5.1 Overview of the Instruction and
Page 49 and 50: 5.3 IDC Enable/Disable and Reset Th
Page 51 and 52: 6.1 Overview Note 6.1.1 Bufferable

ARM710T processor

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