digital compensation of dynamic acquisition errors at the front-end of ...

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List of Figures Figure 1.1: Block diagram of the receiver architecture in wireless base stations. (a) Conventional receiver using ADCs at baseband. (b) Using IF subsampling in the receiver architecture. ........................................................................2 Figure 1.2: Applying the inverse nonlinear function to the ADC output for compensation of dynamic nonlinearities at its front-end.........................4 Figure 2.1: Block diagram of an analog-to-digital converter, including sampling and quantization. ...............................................................................................8 Figure 2.2: Impact of nonlinearity in distorting the frequency spectrum of the received signal. ..........................................................................................................9 Figure 2.3: Definition of INL and DNL using the ADC’s transfer function..................9 Figure 2.4: SFDR definition using the output frequency spectrum of an ADC. ..........10 Figure 2.5: SFDR performance vs. input frequency, from National ADC14155 [11]. 11 Figure 2.6: Block diagram of the ADC’s front-end including input driving circuit and the acquisition stage. .................................................................................12 Figure 2.7: A simple track-and-hold stage at the acquisition stage of the ADC..........12 Figure 2.8: Block diagram of the ADC together with the input driving circuit. (a) Input driving circuit using a transformer. (b) Input driving circuit using a buffer or differential amplifiers.............................................................................13 Figure 2.9: Ideal and real output of a track-and-hold stage during tracking and hold phases. .......................................................................................................14 Figure 2.10: Charge injection in a track-and-hold circuit. ...........................................15 Figure 2.11: Simplified model for charge injection [24]..............................................17 xiv
Figure 2.12: Ratio of charge injection into source and drain of transistor vs. clock fall time. .........................................................................................................17 Figure 2.13: A bottom-plate track-and-hold circuit. ....................................................18 Figure 2.14: Deviation from a straight line in the plot of charge injection vs. input voltage. Total charge is defined as the charge on the capacitor at full scale, Q total =2pF×1V=2e -12 C. .................................................................20 Figure 2.15: Charge injection nonlinearity in a bottom-plate track-and-hold vs. different circuit parameters (equation (2.3)). (a) Linearity vs. size of M 2 (W 2 ). (b) Linearity vs. size of M 1 (W 1 ). (c) Linearity vs. size of capacitor. (d) Linearity vs. Clock fall time. ..........................................21 Figure 2.16: Bootstrap circuit for the sampling switch. (a) Bottom-plate track-and-hold with a bootstrap switch. (b) Bootstrap switch structure [32]. ..................23 Figure 2.17: SFDR of the bottom-plate track-and-hold vs. input frequency obtained from AC TCAD simulations...................................................................24 Figure 2.18: Schematic of a flip-around track-and-hold amplifier with bootstrapped switch......................................................................................................25 Figure 2.19: Schematic of the front-end of the ADC including flip-around track-andhold amplifier, package parasitic and the input driving circuit. .............27 Figure 2.20: Current spikes at the input driving circuit caused by charge glitches coming from the sampling capacitor......................................................28 Figure 2.21: Input signal distorted by the ringing caused by parasitic inductances (L par =3 nH, C S =3 pF, C par =6 pF )...........................................................28 Figure 2.22: Simple model for the input circuit and the track-and-hold. .....................29 Figure 2.23: Model of the track-and-hold, input driving circuit and package parasitics. ..................................................................................................................31 Figure 2.24: Schematic of a real transformer model with its parasitics. ......................32 Figure 2.25: Basic model for the input circuit including buffer/amplifier. ..................34 xv
Page 1 and 2: DIGITAL COMPENSATION OF DYNAMIC ACQ
Page 3: I certify that I have read this dis
Page 6 and 7: apply the inverse nonlinear functio
Page 8 and 9: Dr. Echere Iroaga, Dr. Yangjin Oh,
Page 10 and 11: Table of Contents Abstract.........
Page 12 and 13: 4.3.3 Algorithm performance on diff
Page 16 and 17: Figure 3.1: Block diagram of ADC er
Page 18 and 19: Figure 4.4: Frequency spectrum of t
Page 21 and 22: Chapter 1 Introduction 1.1 Motivati
Page 23 and 24: Chapter 1: Introduction 3 cancel th
Page 25 and 26: Chapter 1: Introduction 5 to correc
Page 27 and 28: Chapter 2 Nonlinearity at the ADC
Page 29 and 30: Chapter 2: Nonlinearity at the ADC
Page 57 and 58: Chapter 3 Digital Correction of Dyn
Page 59 and 60: Chapter 3: Digital Correction of Dy
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Chapter 3: Digital Correction of Dy
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Chapter 4 Experimental Results In t
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Chapter 4: Experimental Results 67
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Chapter 5 Impact of Substrate Noise
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Chapter 5: Impact of Substrate Nois
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Chapter 6 Conclusion 6.1 Summary IF
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Chapter 6: Conclusion 95 very sensi
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Chapter 6: Conclusion 97 the desire
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Appendix A TCAD Simulation of a Tra
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Appendix A: TCAD Simulation of Trac
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Appendix A: TCAD Simulation of Trac
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Appendix B Modeling Signal Derivati
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Appendix B: Modeling Signal Derivat
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Appendix C Coefficient Calibration
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Appendix C: Coefficient Calibration
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Bibliography [1] A.M.A. Ali et al.,
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Bibliography 115 [23] J. Kuo, R. Du
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Bibliography 117 [46] F. H. Irons,
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Bibliography 119 [68] B. Razavi, B.
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