digital compensation of dynamic acquisition errors at the front-end of ...

16 Chapter 2: Nonlinearity at the ADC’s Front-End
The other source of charge injection during transition from tracking to hold mode
is the charge in the transistor channel. Using square law device models, this charge
can approximately be modeled as
Q
ch
= C Φ − ( V −V
)]
(2.2)
ch[ H gs th
When the switch turns off, a fraction of the transistor channel charge goes toward the
source and drain terminals depending on the impedance seen at these nodes and also
the clock fall time. This charge strongly depends on the input and can cause significant
distortion to the sampled value.
Several studies have been done in the past years to analyze what defines the
fraction of charge going to each terminal and how it can be calculated [23]-[28]. For a
slow clock fall time, the channel conductance follows the gate voltage and the circuit
can be modeled as shown in Figure 2.11 [24]. The charge injection in this block can be
analyzed by writing the differential equation and finding its solution through
numerical methods. If the clock fall time is faster than the carrier transit time in the
channel, the two ends of the channel pinch off at the beginning of the clock fall time
and the terminal voltages do not have any effect on the charge distribution. This
causes the charge to split equally between the source and drain terminal of the device.
Figure 2.12 shows the ratio of the charge going to source and drain of the transistor
versus their clock fall time and the ratio of the capacitor sizes at the two terminals.
This figure was obtained by simulating the circuit of Figure 2.11 in HSpice (using a
TSMC 130-nm process) for different clock fall time and capacitor sizes (similar to the
plot in [24]). As can be observed from this figure, most of the channel charge flows to
the terminal with larger capacitance for slow clock fall times; the charge splits equally
between the two terminals at very fast clock fall times.