digital compensation of dynamic acquisition errors at the front-end of ...

Figure 3.12: (a) Frequency response of the bandpass filter used for reconstructing
interpolated samples with upsampling factor of K=100 located in the 3 rd
Nyquist zone. (b) Bandpass filter from the 1 st to the 10 th Nyquist zone 53
Figure 3.13: Error in the corrected output vs. number of interpolated samples used in
the model.................................................................................................54
Figure 3.14: SFDR vs. input frequency in the first 4 Nyquist zones (f clk =100 MHz)
before and after digital enhancement, using interpolated samples in the
model. (a) SFDR in the1 st Nyquist zone. (b) SFDR in the 2 nd Nyquist
zone. (c) SFDR in the 3 rd Nyquist zone. (d) SFDR in the 4 th Nyquist
zone.........................................................................................................55
Figure 3.15: Results of applying the algorithm in simulation to the nonlinear model of
the track-and-hold with two-tone or three-tone signals. (a) Input signal
located at 263 MHz and 273 MHz. (b) Input signals located at 263 MHz,
273 MHz and 291 MHz...........................................................................56
Figure 3.16: Applying correction algorithm on an arbitrary signal including nine single
tone sinewaves located at the 5 th Nyquist zone........................................58
Figure 3.17: Frequency spectrum at the track-and-hold output with quantization noise
and 8 LSB of random noise before and after digital correction (f in =263
MHz, f clk =100 MHz). (a) Before digital correction. (b) After digital
correction. ...............................................................................................59
Figure 3.18: Circuit diagram of the ADC front-end including flip-around track-andhold
amplifier, package parasitics and the input driving circuit including
transformer. ............................................................................................61
Figure 3.19: Frequency spectrum at the output of the ADC front-end simulation before
and after digital enhancement. (a) f in =326 MHz. (b)f in =898 MHz. .........62
Figure 4.1: Photo of the ADC test setup with the data capture board. .........................65
Figure 4.2: Block diagram of the test setup..................................................................66
Figure 4.3: Block diagram of the digital post processor. .............................................68
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