digital compensation of dynamic acquisition errors at the front-end of ...

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Figure 4.4: Frequency spectrum of the ADC output at f in =326 MHz (f clk =155 MHz). 70 Figure 4.5: SFDR vs. input frequency in the 5 th and 6 th Nyquist zone (f clk =155 MHz). ..................................................................................................................71 Figure 4.6: Block diagram of the test setup used for temperature variation measurement. PD is an unused pin on the chip and is connected to a negative voltage through a resistor in order to forward bias the ESD diode.......................................................................................................72 Figure 4.7: SFDR of the ADC vs. temperature variations (f in =326 MHz, f clk =155 MHz)........................................................................................................73 Figure 4.8: Variations in switch resistance nonlinear terms vs. temperature...............75 Figure 4.9: SFDR vs. input frequency in the 11 th Nyquist zone for the ADS6143......76 Figure 4.10: Block diagram of the ADC with the input driving circuit optimized for low frequency tests [60]..........................................................................77 Figure 4.11: SFDR of the National ADC14155 vs. input frequency in the 5 th Nyquist zone. The input circuit has been modified to cause more distortion. .....78 Figure 4.12: Block diagram of the ADC together with a DVGA [61]. ........................78 Figure 4.13: SFDR of the ADC together with DVGA in the 5 th Nyquist zone............79 Figure 4.14: A comparison between SFDR performance of the state-of-the-art high resolution ADCs and the result of this work...........................................80 Figure 5.1: Noise injection and propagation in the substrate. ......................................82 Figure 5.2: Block diagram of the flash ADC. ..............................................................83 Figure 5.3: Block diagram of the comparator architecture...........................................84 Figure 5.4: Latch output before and after noise coupling. ...........................................87 Figure 5.5: Die photo and layout of the test chip. ........................................................88 Figure 5.6: Block diagram of the digital noise emulator (DNE)..................................88 Figure 5.7: Block diagram of the toggling test structure..............................................89 xviii
Figure 5.8: a) INL and DNL of the ADC. b) SNDR of the ADC vs. clock and input frequencies. ...............................................................................................90 Figure 5.9: SNDR of the ADC vs. noise frequency. ....................................................91 Figure 5.10: (a) Comparator output jitter vs. noise frequency for two clk frequencies, (b) Comparator jitter vs. noise frequency for DNEs at two different locations...................................................................................................91 Figure 6.1: Block diagram of the background calibration scheme...............................96 Figure A.1: Bottom-plate track-and-hold circuit……………………………………..99 Figure B.1: a) Sub-sampled signal in the time domain. b) Frequency spectrum of a sub-sampled signal……………………………………………………..106 Figure C.1: Convergence of three of the coefficients in H n using 1000 sample points from each sinewave…………………………………………………….111 xix
Page 1 and 2: DIGITAL COMPENSATION OF DYNAMIC ACQ
Page 3: I certify that I have read this dis
Page 6 and 7: apply the inverse nonlinear functio
Page 8 and 9: Dr. Echere Iroaga, Dr. Yangjin Oh,
Page 10 and 11: Table of Contents Abstract.........
Page 12 and 13: 4.3.3 Algorithm performance on diff
Page 14 and 15: List of Figures Figure 1.1: Block d
Page 16 and 17: Figure 3.1: Block diagram of ADC er
Page 21 and 22: Chapter 1 Introduction 1.1 Motivati
Page 23 and 24: Chapter 1: Introduction 3 cancel th
Page 25 and 26: Chapter 1: Introduction 5 to correc
Page 27 and 28: Chapter 2 Nonlinearity at the ADC
Page 29 and 30: Chapter 2: Nonlinearity at the ADC
Page 57 and 58: Chapter 3 Digital Correction of Dyn
Page 59 and 60: Chapter 3: Digital Correction of Dy
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Chapter 3: Digital Correction of Dy
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Chapter 4 Experimental Results In t
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Chapter 4: Experimental Results 67
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Chapter 5 Impact of Substrate Noise
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Chapter 5: Impact of Substrate Nois
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Chapter 6 Conclusion 6.1 Summary IF
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Chapter 6: Conclusion 95 very sensi
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Chapter 6: Conclusion 97 the desire
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Appendix A TCAD Simulation of a Tra
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Appendix A: TCAD Simulation of Trac
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Appendix A: TCAD Simulation of Trac
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Appendix B Modeling Signal Derivati
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Appendix B: Modeling Signal Derivat
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Appendix C Coefficient Calibration
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Appendix C: Coefficient Calibration
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Bibliography [1] A.M.A. Ali et al.,
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Bibliography 115 [23] J. Kuo, R. Du
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Bibliography 117 [46] F. H. Irons,
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Bibliography 119 [68] B. Razavi, B.
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