digital compensation of dynamic acquisition errors at the front-end of ...

Abstract
In Analog-to-Digital Converter (ADC) applications such as wireless base stations,
sub-sampling at an Intermediate Frequency (IF) is an attractive method for minimizing
component count and system cost. By applying this method, one or more steps of
down-conversion are removed from the receiver path and some of the analog front-end
signal processing functions can be moved to the digital domain. In such a solution, the
ADC’s linearity at high input frequencies becomes a critical issue. Despite the use of a
dedicated track-and-hold amplifier (THA), nonlinearities in the circuit’s input network
often introduce dynamic errors that limit the performance of the ADC at high input
frequencies.
A number of analog techniques have been proposed in the past to improve the
linearity performance of the ADC’s front-end. However, most of these techniques
suffer from bandwidth limitations in the active analog circuitry and lose their
performance at high input frequencies. In recent years, the continuous scaling of
CMOS technology has resulted in low cost and high performance digital circuits. This
has provided the feasibility to integrate complicated digital signal processing on chip
and therefore use digital correction methods to compensate circuit nonlinearities in
ADCs. However, these techniques mainly address static errors in the converter core
and are not effective at removing dynamic nonlinearities at the front-end of the ADC.
This dissertation introduces a digital enhancement scheme that is specifically
tailored to remove high frequency distortion caused by the dynamic nonlinearities at
the sampling front-end of ADCs. The basic concept of digital compensation here is to
v