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10 Chapter 2: Nonlinearity at the ADC’s Front-End Figure 2.4: SFDR definition using the output frequency spectrum of an ADC. 2.2 Overview of ADC linearity limitations ADCs used in communication applications usually need to sample signals at high frequencies. As explained in the previous section, it is also very important in these applications to add the least amount of distortion to the received signal during the digitization process. Therefore, the SFDR of these ADCs over their input bandwidth is an important factor defining the performance of the system. The linearity of ADCs usually drops significantly with increasing input frequency. This can be observed as the degradation in their SFDR performance over the input frequency bandwidth as shown in Figure 2.5. This figure shows an SFDR plot of a state-of-the art 14-bit ADC [11] over its input bandwidth. The drop in linearity performance is due to the frequency dependent nonlinear errors generated in the transfer function of the ADC. Frequency dependent nonlinearities are caused by nonlinear functions with memory.
Chapter 2: Nonlinearity at the ADC’s Front-End 11 Figure 2.5: SFDR performance vs. input frequency, from National ADC14155 [11]. The nonlinear error generated in the ADC core (see Figure 2.1) is mainly the result of non-ideal quantization and is a static nonlinearity. This error is reflected in the INL/DNL performance of the ADC and also in its SFDR performance at low input frequencies [14]. These static nonlinear errors have been investigated extensively in the literature and several methods exist for minimizing and compensating them [15]- [18]. The linearity at high input frequencies is mainly limited by dynamic errors generated at the ADC’s front-end, including the input driving circuit and the acquisition stage (see Figure 2.6). The acquisition stage is usually the most significant source of dynamic nonlinear error at the front-end of ADC. This stage includes a track-and-hold circuit consisting of a sampling switch and a capacitor, as shown in Figure 2.7, and is in charge of sampling the continuous-time input signal and converting it to discrete-time sample points. The input driving circuit can be another source of dynamic errors at the ADC’s front-end when used together with the acquisition stage. The driver can include a transformer for converting single-ended to differential signals (see Figure 2.8(a)), or it
Page 1 and 2: DIGITAL COMPENSATION OF DYNAMIC ACQ
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Page 10 and 11: Table of Contents Abstract.........
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Chapter 3: Digital Correction of Dy
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Chapter 3: Digital Correction of Dy
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Chapter 4 Experimental Results In t
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Chapter 4: Experimental Results 67
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Chapter 5 Impact of Substrate Noise
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Chapter 5: Impact of Substrate Nois
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Chapter 6 Conclusion 6.1 Summary IF
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Chapter 6: Conclusion 95 very sensi
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Chapter 6: Conclusion 97 the desire
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Appendix A TCAD Simulation of a Tra
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Appendix A: TCAD Simulation of Trac
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Appendix A: TCAD Simulation of Trac
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Appendix B Modeling Signal Derivati
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Appendix B: Modeling Signal Derivat
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Appendix C Coefficient Calibration
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Appendix C: Coefficient Calibration
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Bibliography [1] A.M.A. Ali et al.,
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Bibliography 115 [23] J. Kuo, R. Du
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Bibliography 117 [46] F. H. Irons,
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Bibliography 119 [68] B. Razavi, B.
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