digital compensation of dynamic acquisition errors at the front-end of ...

4 Chapter 1: Introduction
linearity performance (SFDR>83 dB) in the ADC at high input frequencies (f in =470
MHz).
V
out
( k) = f [ V ( k) , V ( k −1 ),...]
nonlin
in
in
D
out
, corrected
= gnonlin[
Dout
( k),
Dout
( k −1),...]
Figure 1.2: Applying the inverse nonlinear function to the ADC output for
compensation of dynamic nonlinearities at its front-end.
1.2 Organization
This thesis is organized into six chapters of which this is the first. Chapter 2
introduces the sources of nonlinearity at the front-end of ADCs and shows how
judicious modeling of these imperfections helps us simplify the correction process.
The analysis in this chapter shows where the memory and nonlinearities at the
acquisition stage of the ADC are coming from and how they affect the linearity
performance of the system. A compact nonlinear model is developed and it is
expanded to take nonidealities of the ADC’s input driving circuit into account.
Our proposed digital correction algorithm is presented in Chapter 3. Several
approaches for calibrating the filter coefficients and also simplifying the correction
process are discussed and results of applying them to the nonlinear model of a trackand-hold
circuit are presented. The simulation results show that the algorithm is
capable of significantly increasing the linearity of the ADC’s front-end. It can be used