ARM Processor Instruction Set

ARM Processor Instruction Set
5.5 PSR transfer (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are
defined in ➲5.2 The condition field on page 5-3.
The MRS and MSR instructions are formed from a subset of the Data Processing
operations and are implemented using the TEQ, TST, CMN and CMP instructions
without the S flag set. The encoding is shown in ➲Figure 5-12: PSR transfer on page
5-16.
These instructions allow access to the CPSR and SPSR registers. The MRS
instruction allows the contents of the CPSR or SPSR_ to be moved to a
general register.
The MSR instruction allows the contents of a general register to be moved to the
CPSR or SPSR_ register. The MSR instruction also allows an immediate
value or register contents to be transferred to the condition code flags (N,Z,C and V)
of CPSR or SPSR_ without affecting the control bits. In this case, the top four
bits of the specified register contents or 32-bit immediate value are written to the top
four bits of the relevant PSR.
5.5.1 Operand restrictions
Note:
In User mode, the control bits of the CPSR are protected from change, so only the
condition code flags of the CPSR can be changed. In other (privileged) modes the
entire CPSR can be changed.
The SPSR register which is accessed depends on the mode at the time of execution.
For example, only SPSR_fiq is accessible when the processor is in FIQ mode.
R15 must not be specified as the source or destination register.
A further restriction is that you must not attempt to access an SPSR in User mode,
since no such register exists.
Preliminary - Unrestricted
ARM7500 Data Sheet
ARM DDI 0050C
5-15