ARM Processor Instruction Set

ARM Processor Instruction Set
5.8.8 Instruction cycle times
Instruction
Normal LDM instructions
LDM PC
STM instructions
Cycles
1 instruction fetch, n data reads and 1 internal cycle
3 instruction fetches, n data reads and 1 internal cycle.
instruction fetch, n data reads and 1 internal cycle, where n is the
number of words transferred.
5.8.9 Assembler syntax
Table 5-5: Instruction cycle times
For more information see ➲5.16.7 Instruction speed summary on page 5-55.
{cond} Rn{!},{^}
{cond} - two character condition mnemonic, see ➲Figure 5-2: Condition codes on page
5-3
Preliminary - Unrestricted
Rn is an expression evaluating to a valid register number
is a list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}).
{!} if present requests write-back (W=1), otherwise W=0
{^} if present set S bit to load the CPSR along with the PC, or force transfer of user
bank when in privileged mode
5-34
ARM7500 Data Sheet
ARM DDI 0050C