ARM Processor Instruction Set

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ARM Processor Instruction Set 5.8.2 Addressing modes The transfer addresses are determined by : • the contents of the base register (Rn) • the pre/post bit (P) • the up/down bit (U) The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). ➲Figure 5-17: Post-increment addressing, ➲Figure 5-18: Pre-increment addressing, ➲Figure 5-19: Post-decrement addressing, and ➲Figure 5-20: Pre-decrement addressing on page 5-32, show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. Preliminary - Unrestricted 5.8.3 Address alignment In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. The address should always be a word aligned quantity. R n 1 R5 R1 0x100C 0x1000 0x0FF4 0x100C 0x1000 Rn R1 2 R7 R5 R1 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x0FF4 3 4 Figure 5-17: Post-increment addressing 5-30 ARM7500 Data Sheet ARM DDI 0050C
ARM Processor Instruction Set 0x100C 0x100C R1 Rn 0x1000 0x1000 0x0FF4 0x0FF4 1 2 0x100C Rn R7 0x100C R5 R5 R1 R1 0x1000 0x1000 0x0FF4 0x0FF4 Rn 3 1 0x100C 0x1000 0x0FF4 0x100C 0x1000 4 Figure 5-18: Pre-increment addressing 0x100C 0x1000 R1 0x0FF4 2 0x100C R7 0x1000 Preliminary - Unrestricted R5 R5 R1 R1 0x0FF4 Rn 0x0FF4 3 4 Figure 5-19: Post-decrement addressing ARM7500 Data Sheet ARM DDI 0050C 5-31
Page 1 and 2: 1 11 5 ARM Processor Instruction Se
Page 3 and 4: ARM Processor Instruction Set 5.2 T
Page 5 and 6: ARM Processor Instruction Set 5.3.3
Page 7 and 8: ARM Processor Instruction Set . 31
Page 9 and 10: If the S bit is set (and Rd is not
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Page 15 and 16: ARM Processor Instruction Set 5.5 P
Page 23 and 24: 5.7 Single data transfer (LDR, STR)
Page 25 and 26: ARM Processor Instruction Set Littl
Page 29: 5.8 Block data transfer (LDM, STM)
Page 37 and 38: ARM Processor Instruction Set 5.9 S
Page 39 and 40: ARM Processor Instruction Set 5.10
Page 43 and 44: ARM Processor Instruction Set 5.12.
Page 49 and 50: 5.14.2 Transfers to R15 5.14.3 Tran
Page 53 and 54: ARM Processor Instruction Set BCC D
Page 55 and 56: ARM Processor Instruction Set ; Not
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ARM Processor Instruction Set

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